Inventor
GUERON SHAY
IL130 patents
⚠️ This page may combine multiple inventors who share the name “GUERON SHAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS9960907B2May 1, 2018
Instruction for Performing SIMD affine transformation
INTEL CORP89 citations99
US9906359B2Feb 27, 2018
Instructions and logic to provide general purpose GF(256) SIMD cryptographic arithmetic functionality
INTEL CORP90 citations99
US7949130B2May 24, 2011
Architecture and instruction set for implementing advanced encryption standard (AES)
INTEL CORP54 citations99
US9766888B2Sep 19, 2017
Processor instruction to store indexes of source data elements in positions representing a sorted order of the source data elements
INTEL CORP23 citations94
US9230120B2Jan 5, 2016
Architecture and instruction set for implementing advanced encryption standard (AES)
INTEL CORP12 citations93
US10560259B2Feb 11, 2020
Architecture and instruction set for implementing advanced encryption standard (AES)
INTEL CORP2 citations84
US10554387B2Feb 4, 2020
Architecture and instruction set for implementing advanced encryption standard (AES)
INTEL CORP2 citations84
US10432393B2Oct 1, 2019
Architecture and instruction set for implementing advanced encryption standard (AES)
INTEL CORP2 citations84
US10256971B2Apr 9, 2019
Flexible architecture and instruction for advanced encryption standard (AES)
INTEL CORP2 citations84
US9990314B2Jun 5, 2018
Instructions and logic to interrupt and resume paging in a secure enclave page cache
INTEL CORP7 citations84
US9703733B2Jul 11, 2017
Instructions and logic to interrupt and resume paging in a secure enclave page cache
INTEL CORP5 citations84
US9513913B2Dec 6, 2016
SM4 acceleration processors, methods, systems, and instructions
INTEL CORP5 citations84
US9317719B2Apr 19, 2016
SM3 hash algorithm acceleration processors, methods, systems, and instructions
INTEL CORP9 citations84
US9047082B2Jun 2, 2015
Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations
INTEL CORP7 citations84
US9043604B2May 26, 2015
Method and apparatus for key provisioning of hardware devices
INTEL CORP12 citations84
US8364975B2Jan 29, 2013
Methods and apparatus for protecting data
INTEL CORP12 citations84
US8010587B2Aug 30, 2011
Random number generator
INTEL CORP7 citations84
US7991152B2Aug 2, 2011
Speeding up Galois Counter Mode (GCM) computations
INTEL CORP7 citations84
US10372625B2Aug 6, 2019
Secure memory
INTEL CORP7 citations83
US7958320B2Jun 7, 2011
Protected cache architecture and secure programming paradigm to protect applications
INTEL CORP5 citations74
US11687681B2Jun 27, 2023
Multi-tenant cryptographic memory isolation
INTEL CORP2 citations73
US11563556B2Jan 24, 2023
Architecture and instruction set for implementing advanced encryption standard (AES)
INTEL CORP0 citations73
US11128443B2Sep 21, 2021
SM3 hash algorithm acceleration processors, methods, systems, and instructions
INTEL CORP3 citations73
US11075746B2Jul 27, 2021
SM3 hash algorithm acceleration processors, methods, systems, and instructions
INTEL CORP1 citations73
US10776525B2Sep 15, 2020
Multi-tenant cryptographic memory isolation
INTEL CORP4 citations73
US10623175B2Apr 14, 2020
SM3 hash algorithm acceleration processors, methods, systems, and instructions
INTEL CORP1 citations73
US10476667B2Nov 12, 2019
SM4 acceleration processors, methods, systems, and instructions
INTEL CORP1 citations73
US10469249B2Nov 5, 2019
SM4 acceleration processors, methods, systems, and instructions
INTEL CORP1 citations73
US10447468B2Oct 15, 2019
SM4 acceleration processors, methods, systems, and instructions
INTEL CORP1 citations73
US10425222B2Sep 24, 2019
SM4 acceleration processors, methods, systems, and instructions
INTEL CORP1 citations73
GUERON SHAY
10 patentsUS8634550B2Jan 21, 2014
Architecture and instruction set for implementing advanced encryption standard (AES)
GUERON SHAY37 citations98
US8407425B2Mar 26, 2013
Obscuring memory access patterns in conjunction with deadlock detection or avoidance
GUERON SHAY44 citations98
US8538015B2Sep 17, 2013
Flexible architecture and instruction for advanced encryption standard (AES)
GUERON SHAY40 citations97
US8340280B2Dec 25, 2012
Using a single instruction multiple data (SIMD) instruction to speed up galois counter mode (GCM) computations
GUERON SHAY46 citations94
US9076019B2Jul 7, 2015
Method and apparatus for memory encryption with integrity check and protection against replay attacks
GUERON SHAY9 citations84
US8856546B2Oct 7, 2014
Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures
GUERON SHAY14 citations84
US8600049B2Dec 3, 2013
Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
GUERON SHAY8 citations84
US8468365B2Jun 18, 2013
Tweakable encryption mode for memory encryption with protection against replay attacks
GUERON SHAY10 citations84
US8194854B2Jun 5, 2012
Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel modes of operation
GUERON SHAY11 citations84
US8150031B2Apr 3, 2012
Method and apparatus to perform redundant array of independent disks (RAID) operations
GUERON SHAY10 citations84
AMAZON TECH INC
3 patentsRAIKIN SHLOMO
2 patentsKUMAR MOHAN J
2 patentsDIXON MARTIN
1 patentHERBERT HOWARD C
1 patentMATHEW SANU K
1 patentShowing the top 50 of 130 patents by PatentIndex Score.