Inventor · disambiguated record
Simon C. Steely, Jr.
Also filed as: STEELY JR SIMON · STEELY JR SIMON C · STEELY SIMON · STEELY SIMON C
132 granted patents·21 pending applications·3,594 citations·filing 1982–2025
99Inventor score
Files withINTEL CORP56HEWLETT PACKARD DEVELOPMENT CO25DIGITAL EQUIPMENT CORP20COMPAQ COMPUTER CORP17STEELY JR SIMON C12
Top patents by PatentIndex Score
153 records- 0198US10515049B1Memory circuits and methods for distributed memory hazard detection and error recoveryINTEL CORP·Filed 2017·Granted Dec 24, 2019·32 cites·24 claims
- 0298US10275243B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2016·Granted Apr 30, 2019·23 cites·20 claims
- 0397US10467183B2Processors and methods for pipelined runtime services in a spatial arrayINTEL CORP·Filed 2017·Granted Nov 5, 2019·28 cites·24 claims
- 0496US11698787B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2021·Granted Jul 11, 2023·3 cites·17 claims
- 0596US10515046B2Processors, methods, and systems with a configurable spatial acceleratorINTEL CORP·Filed 2017·Granted Dec 24, 2019·18 cites·24 claims
- 0695US11593295B2Apparatuses, methods, and systems for operations in a configurable spatial acceleratorINTEL CORP·Filed 2021·Granted Feb 28, 2023·6 cites·24 claims
- 0795US11200186B2Apparatuses, methods, and systems for operations in a configurable spatial acceleratorINTEL CORP·Filed 2018·Granted Dec 14, 2021·11 cites·24 claims
- 0893US10915471B2Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial acceleratorINTEL CORP·Filed 2019·Granted Feb 9, 2021·8 cites·24 claims
- 0993US10678724B1Apparatuses, methods, and systems for in-network storage in a configurable spatial acceleratorINTEL CORP·Filed 2018·Granted Jun 9, 2020·13 cites·24 claims
- 1093US10445098B2Processors and methods for privileged configuration in a spatial arrayINTEL CORP·Filed 2017·Granted Oct 15, 2019·10 cites·24 claims
- 1192US11086816B2Processors, methods, and systems for debugging a configurable spatial acceleratorINTEL CORP·Filed 2017·Granted Aug 10, 2021·9 cites·20 claims
- 1292US10572376B2Memory ordering in acceleration hardwareINTEL CORP·Filed 2016·Granted Feb 25, 2020·9 cites·24 claims
- 1392US10474375B2Runtime address disambiguation in acceleration hardwareINTEL CORP·Filed 2016·Granted Nov 12, 2019·9 cites·24 claims
- 1492US10402176B2Methods and apparatus to compile code to generate data flow codeINTEL CORP·Filed 2017·Granted Sep 3, 2019·11 cites·15 claims
- 1592US7725657B2Dynamic quality of service (QoS) for a shared cacheINTEL CORP·Filed 2007·Granted May 25, 2010·33 cites·17 claims
- 1691US10445451B2Processors, methods, and systems for a configurable spatial accelerator with performance, correctness, and power reduction featuresINTEL CORP·Filed 2017·Granted Oct 15, 2019·8 cites·2 claims
- 1791US10416999B2Processors, methods, and systems with a configurable spatial acceleratorINTEL CORP·Filed 2016·Granted Sep 17, 2019·8 cites·24 claims
- 1891US10387319B2Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support featuresINTEL CORP·Filed 2017·Granted Aug 20, 2019·9 cites·10 claims
- 1991US10380063B2Processors, methods, and systems with a configurable spatial accelerator having a sequencer dataflow operatorINTEL CORP·Filed 2017·Granted Aug 13, 2019·13 cites·24 claims
- 2091US6647466B2Method and apparatus for adaptively bypassing one or more levels of a cache hierarchyHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 11, 2003·68 cites·22 claims
- 2191US6055605ATechnique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared cachesCOMPAQ COMPUTER CORP·Filed 1997·Granted Apr 25, 2000·181 cites·17 claims
- 2291US5758142ATrainable apparatus for predicting instruction outcomes in pipelined processorsDIGITAL EQUIPMENT CORP·Filed 1994·Granted May 26, 1998·176 cites·31 claims
- 2390US11656662B2Layered super-reticle computing : architectures and methodsINTEL CORP·Filed 2021·Granted May 23, 2023·2 cites·19 claims
- 2489US10496574B2Processors, methods, and systems for a memory fence in a configurable spatial acceleratorINTEL CORP·Filed 2017·Granted Dec 3, 2019·6 cites·5 claims
- 2588US10558575B2Processors, methods, and systems with a configurable spatial acceleratorINTEL CORP·Filed 2016·Granted Feb 11, 2020·7 cites·24 claims
- 2688US10469397B2Processors and methods with configurable network-based dataflow operator circuitsINTEL CORP·Filed 2017·Granted Nov 5, 2019·6 cites·25 claims
- 2788US8407421B2Cache spill management techniques using cache spill predictionSTEELY JR SIMON C·Filed 2009·Granted Mar 26, 2013·17 cites·29 claims
- 2888US6209065B1Mechanism for optimizing generation of commit-signals in a distributed shared-memory systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 27, 2001·144 cites·15 claims
- 2988US6108737AMethod and apparatus for reducing latency of inter-reference ordering in a multiprocessor systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 22, 2000·148 cites·21 claims
- 3088US5519841AMulti instruction register mapperDIGITAL EQUIPMENT CORP·Filed 1992·Granted May 21, 1996·134 cites·18 claims
- 3187US10963022B2Layered super-reticle computing : architectures and methodsINTEL CORP·Filed 2020·Granted Mar 30, 2021·2 cites·25 claims
- 3287US6088771AMechanism for reducing latency of memory barrier operations on a multiprocessor systemDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jul 11, 2000·142 cites·7 claims
- 3387US5197132ARegister mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recoveryDIGITAL EQUIPMENT CORP·Filed 1990·Granted Mar 23, 1993·129 cites·10 claims
- 3487US2025138823A1Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2024·Application pending·0 cites
- 3586US10691182B2Layered super-reticle computing: architectures and methodsINTEL CORP·Filed 2019·Granted Jun 23, 2020·4 cites·25 claims
- 3686US6014690AEmploying multiple channels for deadlock avoidance in a cache coherency protocolDIGITAL EQUIPMENT CORP·Filed 1997·Granted Jan 11, 2000·128 cites·39 claims
- 3785US10445234B2Processors, methods, and systems for a configurable spatial accelerator with transactional and replay featuresINTEL CORP·Filed 2017·Granted Oct 15, 2019·4 cites·18 claims
- 3884US6101420AMethod and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directoriesCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 8, 2000·90 cites·21 claims
- 3983US8533422B2Instruction prefetching using cache line historySUBRAMANIAM SAMANTIKA·Filed 2010·Granted Sep 10, 2013·11 cites·16 claims
- 4083US6801986B2Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operationHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 5, 2004·37 cites·24 claims
- 4183US6085263AMethod and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processorCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 4, 2000·111 cites·18 claims
- 4282US12204898B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·24 claims
- 4382US10445250B2Apparatus, methods, and systems with a configurable spatial acceleratorINTEL CORP·Filed 2017·Granted Oct 15, 2019·3 cites·24 claims
- 4482US7177987B2System and method for responses between different cache coherency protocolsHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Feb 13, 2007·31 cites·33 claims
- 4581US12050912B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2023·Granted Jul 30, 2024·0 cites·20 claims
- 4681US10402168B2Low energy consumption mantissa multiplication for floating point multiply-add operationsINTEL CORP·Filed 2016·Granted Sep 3, 2019·3 cites·24 claims
- 4780US9262327B2Signature based hit-predicting cacheSTEELY JR SIMON C·Filed 2012·Granted Feb 16, 2016·6 cites·26 claims
- 4880US9037804B2Efficient support of sparse data structure accessSTEELY JR SIMON C·Filed 2011·Granted May 19, 2015·5 cites·13 claims
- 4980US6279084B1Shadow commands to optimize sequencing of requests in a switch-based multi-processor systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 21, 2001·96 cites·18 claims
- 5079US10379855B2Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registersINTEL CORP·Filed 2016·Granted Aug 13, 2019·2 cites·23 claims
Showing the top 50 of 153 patent records by PatentIndex Score.
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