Inventor · disambiguated record
Hsiao-Ling Lu
Also filed as: LU HSIAO-LING
8 granted patents·3 pending applications·125 citations·filing 1999–2007
88Inventor score
Top patents by PatentIndex Score
11 records- 0179US6251779B1Method of forming a self-aligned silicide on a semiconductor waferUNITED MICROELECTRONICS CORP·Filed 2000·Granted Jun 26, 2001·28 cites·8 claims
- 0270US6140192AMethod for fabricating semiconductor deviceUNITED MICROELECTRONICS CORP·Filed 1999·Granted Oct 31, 2000·30 cites·16 claims
- 0367US7544305B2Chemical mechanical polishing process for forming shallow trench isolation structureUNITED MICROELECTRONICS CORP·Filed 2007·Granted Jun 9, 2009·2 cites·5 claims
- 0463US6235606B1Method of fabricating shallow trench isolationUNITED MICROELECTRONICS CORP·Filed 1999·Granted May 22, 2001·29 cites·14 claims
- 0559US7294575B2Chemical mechanical polishing process for forming shallow trench isolation structureUNITED MICROELECTRONICS CORP·Filed 2004·Granted Nov 13, 2007·7 cites·6 claims
- 0657US6913978B1Method for forming shallow trench isolation structureUNITED MICROELECTRONICS CORP·Filed 2004·Granted Jul 5, 2005·9 cites·11 claims
- 0755US6661097B1Ti liner for copper interconnect with low-k dielectricIBM·Filed 2002·Granted Dec 9, 2003·7 cites·20 claims
- 0847US6249138B1Method for testing leakage current caused self-aligned silicideUNITED MICROELECTRONICS CORP·Filed 1999·Granted Jun 19, 2001·13 cites·12 claims
- 0939US2006172526A1Method for preventing edge peeling defectUNITED MICROELECTRONICS CORP·Filed 2006·Application pending·0 cites
- 1035US2005085163A1Method for preventing edge peeling defectUNITED MICROELECTRONICS CORP·Filed 2003·Application pending·0 cites
- 1129US2005054277A1Polishing pad and method of polishing waferFiled 2003·Application pending·0 cites
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