Inventor · disambiguated record
Tuan M. Quach
Also filed as: QUACH TUAN · QUACH TUAN M
18 granted patents·2 pending applications·176 citations·filing 1994–2016
94Inventor score
Top patents by PatentIndex Score
20 records- 0188US9990246B2Memory systemINTEL CORP·Filed 2013·Granted Jun 5, 2018·6 cites·18 claims
- 0285US10747605B2Method and apparatus for providing a host memory controller write credits for write commandsINTEL CORP·Filed 2016·Granted Aug 18, 2020·4 cites·25 claims
- 0376US10795755B2Method and apparatus for performing error handling operations using error signalsINTEL CORP·Filed 2016·Granted Oct 6, 2020·2 cites·16 claims
- 0476US10579462B2Method and apparatus for using an error signal to indicate a write request error and write request acceptanceINTEL CORP·Filed 2016·Granted Mar 3, 2020·1 cites·20 claims
- 0576US9852021B2Method and apparatus for encoding registers in a memory moduleINTEL CORP·Filed 2015·Granted Dec 26, 2017·3 cites·18 claims
- 0674US7093079B2Snoop filter bypassINTEL CORP·Filed 2002·Granted Aug 15, 2006·19 cites·19 claims
- 0767US10198306B2Method and apparatus for a memory module to accept a command in multiple partsINTEL CORP·Filed 2015·Granted Feb 5, 2019·1 cites·21 claims
- 0865US5950220AMethod and apparatus for providing a logical double sided memory element by mapping single sided memory elements onto a logical double sided memory address spaceINTEL CORP·Filed 1996·Granted Sep 7, 1999·25 cites·11 claims
- 0962US7054974B2System for end of interrupt handlingINTEL CORP·Filed 2004·Granted May 30, 2006·8 cites·10 claims
- 1062US5659709AWrite-back and snoop write-back buffer to prevent deadlock and to enhance performance in an in-order protocol multiprocessing busAST RESEARCH INC·Filed 1994·Granted Aug 19, 1997·41 cites·6 claims
- 1161US8842490B2Apparatus and method for selectively using a memory command clock as a reference clockQUACH TUAN M·Filed 2012·Granted Sep 23, 2014·4 cites·27 claims
- 1258US7617329B2Programmable protocol to support coherent and non-coherent transactions in a multinode systemINTEL CORP·Filed 2002·Granted Nov 10, 2009·6 cites·30 claims
- 1358US6192442B1Interrupt controllerINTEL CORP·Filed 1998·Granted Feb 20, 2001·39 cites·26 claims
- 1455US7219167B2Accessing configuration registers by automatically changing an indexINTEL CORP·Filed 2003·Granted May 15, 2007·5 cites·24 claims
- 1554US7779211B2Reducing latency in responding to a snoop requestINTEL CORP·Filed 2007·Granted Aug 17, 2010·1 cites·14 claims
- 1646US7308510B2Method and apparatus for avoiding live-lock in a multinode systemINTEL CORP·Filed 2003·Granted Dec 11, 2007·0 cites·12 claims
- 1743US2016092353A1Establishing cold storage pools from aging memorySWANSON ROBERT C·Filed 2014·Application pending·0 cites
- 1842US2004128351A1Mechanism to broadcast transactions to multiple agents in a multi-node systemINTEL CORP·Filed 2002·Application pending·0 cites
- 1940US6754754B1Apparatus and method for end of interrupt handlingINTEL CORP·Filed 1999·Granted Jun 22, 2004·11 cites·6 claims
- 2037US8787110B2Realignment of command slots after clock stop exitQUACH TUAN M·Filed 2012·Granted Jul 22, 2014·0 cites·25 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →