Inventor · disambiguated record
Peter Sassone
Also filed as: SASSONE PETER · SASSONE PETER G · SASSONE PETER GENE
9 granted patents·9 pending applications·31 citations·filing 2006–2023
82Inventor score
Top patents by PatentIndex Score
18 records- 0187US7620781B2Efficient Bloom filterINTEL CORP·Filed 2006·Granted Nov 17, 2009·23 cites·25 claims
- 0268US9367468B2Data cache way predictionQUALCOMM INC·Filed 2013·Granted Jun 14, 2016·2 cites·29 claims
- 0364US9715392B2Multiple clustered very long instruction word processing coreQUALCOMM INC·Filed 2014·Granted Jul 25, 2017·2 cites·24 claims
- 0464US9223714B2Instruction boundary prediction for variable length instruction setINTEL CORP·Filed 2013·Granted Dec 29, 2015·2 cites·19 claims
- 0562US10025711B2Hybrid write-through/write-back cache policy managers, and related systems and methodsSASSONE PETER G·Filed 2012·Granted Jul 17, 2018·2 cites·28 claims
- 0661US11663011B2System and method of VLIW instruction processing using reduced-width VLIW processorQUALCOMM INC·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 0755US10719325B2System and method of VLIW instruction processing using reduced-width VLIW processorQUALCOMM INC·Filed 2017·Granted Jul 21, 2020·0 cites·20 claims
- 0851US2025209132A1Efficient multiply-accumulate units for convolutional neural network processing including max poolingTESLA INC·Filed 2023·Application pending·0 cites
- 0951US2025231742A1Transposing information using shadow latches and active latches for efficient die area in processing systemTESLA INC·Filed 2023·Application pending·0 cites
- 1050US2025191121A1Enhanced fractional interpolation for convolutional processor in autonomous or semi-autonomous systemsTESLA INC·Filed 2023·Application pending·0 cites
- 1149US9304932B2Instruction cache having a multi-bit way prediction maskQUALCOMM INC·Filed 2012·Granted Apr 5, 2016·0 cites·24 claims
- 1248US2025307206A1Efficient selection of single instruction multiple data operations for neural processing unitsTESLA INC·Filed 2023·Application pending·0 cites
- 1347US2025284494A1Enhanced global flags for synchronizing coprocessors in processing systemTESLA INC·Filed 2023·Application pending·0 cites
- 1446US9552033B2Latency-based power mode units for controlling power modes of processor cores, and related methods and systemsQUALCOMM INC·Filed 2014·Granted Jan 24, 2017·0 cites·30 claims
- 1544US2025284767A1Matrix multiplication performed using convolution engine which includes array of processing elementsTESLA INC·Filed 2023·Application pending·0 cites
- 1641US2008244224A1Scheduling a direct dependent instructionSASSONE PETER·Filed 2007·Application pending·0 cites
- 1732US2013185516A1Use of Loop and Addressing Mode Instruction Set Semantics to Direct Hardware PrefetchingSASSONE PETER G·Filed 2012·Application pending·0 cites
- 1832US2013185515A1Utilizing Negative Feedback from Unexpected Miss Addresses in a Hardware PrefetcherSASSONE PETER G·Filed 2012·Application pending·0 cites
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