Inventor · disambiguated record
Jen-Pin Su
Also filed as: SU JEN-PIN
8 granted patents·2 pending applications·82 citations·filing 1999–2013
85Inventor score
Top patents by PatentIndex Score
10 records- 0174US8649210B2DDR PSRAM and data writing and reading methods thereofLIN CHIH-HSIN·Filed 2012·Granted Feb 11, 2014·5 cites·12 claims
- 0273US6862673B2Command order maintenance scheme for multi-in/multi-out FIFO in multi-threaded I/O linksSILICON INTEGRATED SYS CORP·Filed 2001·Granted Mar 1, 2005·26 cites·13 claims
- 0368US6845444B2Method and apparatus for reducing strapping devicesSILICON INTEGRATED SYS CORP·Filed 2001·Granted Jan 18, 2005·13 cites·6 claims
- 0464US6424189B1Apparatus and system for multi-stage event synchronizationSILICON INTEGRATED SYS CORP·Filed 2000·Granted Jul 23, 2002·11 cites·9 claims
- 0553US8705313B2DDR PSRAM and data writing and reading methods thereofMEDIATEK INC·Filed 2013·Granted Apr 22, 2014·1 cites·15 claims
- 0651US6317813B1Method for arbitrating multiple memory access requests in a unified memory architecture via a non unified memory controllerSILICON INTEGRATED SYS CORP·Filed 1999·Granted Nov 13, 2001·26 cites·24 claims
- 0747US7206930B2Method and apparatus for reducing strapping devicesSILICON INTEGRATED SYS CORP·Filed 2004·Granted Apr 17, 2007·0 cites·7 claims
- 0842US2007266263A1Speed adjustment system and method for performing the sameSILICON INTEGRATED SYS CORP·Filed 2006·Application pending·0 cites
- 0940US2004057548A1Quasi-synchronous multi-stage event synchronization apparatusSILICON INTEGRATED SYSTEM CORP·Filed 2002·Application pending·0 cites
- 1037US8593902B2Controller and access method for DDR PSRAM and operating method thereofLIN CHIH-HSIN·Filed 2011·Granted Nov 26, 2013·0 cites·26 claims
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