Inventor · disambiguated record
James Walter Rymarczyk
Also filed as: RYMARCZYK JAMES W · RYMARCZYK JAMES WALTER
10 granted patents·1 pending application·819 citations·filing 1978–2011
92Inventor score
Top patents by PatentIndex Score
11 records- 0196US8028290B2Multiple-core processor supporting multiple instruction set architecturesIBM·Filed 2006·Granted Sep 27, 2011·54 cites·9 claims
- 0294US4200927AMulti-instruction stream branch processing mechanismIBM·Filed 1978·Granted Apr 29, 1980·306 cites·8 claims
- 0392US5166674AMultiprocessing packet switching connection system having provision for error correction and recoveryIBM·Filed 1991·Granted Nov 24, 1992·215 cites·13 claims
- 0489US7401240B2Method for dynamically managing power in microprocessor chips according to present processing demandsIBM·Filed 2004·Granted Jul 15, 2008·52 cites·21 claims
- 0586US5161156AMultiprocessing packet switching connection system having provision for error correction and recoveryIBM·Filed 1990·Granted Nov 3, 1992·122 cites·11 claims
- 0685US8806182B2Multiple-core processor supporting multiple instruction set architecturesRYMARCZYK JAMES WALTER·Filed 2011·Granted Aug 12, 2014·12 cites·13 claims
- 0779US4189768AOperand fetch control improvementIBM·Filed 1978·Granted Feb 19, 1980·41 cites·3 claims
- 0870US7484043B2Multiprocessor system with dynamic cache coherency regionsIBM·Filed 2003·Granted Jan 27, 2009·13 cites·19 claims
- 0967US7647519B2System and computer program product for dynamically managing power in microprocessor chips according to present processing demandsIBM·Filed 2008·Granted Jan 12, 2010·3 cites·22 claims
- 1063US7949008B2Method, apparatus and computer program product for cell phone securityIBM·Filed 2006·Granted May 24, 2011·1 cites·20 claims
- 1152US2008147988A1Multiprocessor System With Dynamic Cache Coherency RegionsIBM·Filed 2008·Application pending·0 cites
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