Inventor · disambiguated record
Sherwood Brannon
Also filed as: BRANNON SHERWOOD
13 granted patents·534 citations·filing 1991–2010
94Inventor score
Top patents by PatentIndex Score
13 records- 0190US6680738B1Single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generatorNEOMAGIC CORP·Filed 2002·Granted Jan 20, 2004·41 cites·9 claims
- 0286US5548786ADynamic bus sizing of DMA transfersIBM·Filed 1994·Granted Aug 20, 1996·128 cites·10 claims
- 0376US5313627AParity error detection and recoveryIBM·Filed 1992·Granted May 17, 1994·71 cites·12 claims
- 0474US5644729ABidirectional data buffer for a bus-to-bus interface unit in a computer systemIBM·Filed 1994·Granted Jul 1, 1997·65 cites·11 claims
- 0573USRE41967ESingle-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generatorISHII TAKATOSHI·Filed 2006·Granted Nov 30, 2010·2 cites·22 claims
- 0672US5544346ASystem having a bus interface unit for overriding a normal arbitration scheme after a system resource device has already gained control of a busIBM·Filed 1994·Granted Aug 6, 1996·58 cites·11 claims
- 0769US5333274AError detection and recovery in a DMA controllerIBM·Filed 1991·Granted Jul 26, 1994·52 cites·15 claims
- 0867USRE43235ESingle-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generatorISHII TAKATOSHI·Filed 2010·Granted Mar 13, 2012·1 cites·28 claims
- 0964US5966728AComputer system and method for snooping date writes to cacheable memory locations in an expansion memory deviceIBM·Filed 1995·Granted Oct 12, 1999·45 cites·15 claims
- 1057US5477242ADisplay adapter for virtual VGA support in XGA native modeIBM·Filed 1994·Granted Dec 19, 1995·21 cites·21 claims
- 1152US5673414ASnooping of I/O bus and invalidation of processor cache for memory data transfers between one I/O device and cacheable memory in another I/O deviceIBM·Filed 1994·Granted Sep 30, 1997·24 cites·17 claims
- 1239US5748920ATransaction queue in a graphics controller chipCIRRUS LOGIC INC·Filed 1995·Granted May 5, 1998·13 cites·20 claims
- 1338US5551009AExpandable high performance FIFO design which includes memory cells having respective cell multiplexorsIBM·Filed 1993·Granted Aug 27, 1996·13 cites·15 claims
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