Inventor · disambiguated record
Balkrishna R. Rashingkar
Also filed as: RASHINGKAR BALKRISHNA · RASHINGKAR BALKRISHNA R · RASHINGKAR BALKRISHNA RAMCHANDRA
12 granted patents·29 citations·filing 2005–2022
86Inventor score
Technology areasG06F
Files withSYNOPSYS INC12
Top patents by PatentIndex Score
12 records- 0184US8893073B2Displaying a congestion indicator for a channel in a circuit design layoutSYNOPSYS INC·Filed 2012·Granted Nov 18, 2014·7 cites·15 claims
- 0281US9460258B2Shaping integrated with power network synthesis (PNS) for power grid (PG) alignmentSYNOPSYS INC·Filed 2013·Granted Oct 4, 2016·7 cites·18 claims
- 0373US10896280B1Netlist abstraction for circuit design floorplanningSYNOPSYS INC·Filed 2019·Granted Jan 19, 2021·2 cites·15 claims
- 0471US8910097B2Netlist abstractionSYNOPSYS INC·Filed 2013·Granted Dec 9, 2014·3 cites·18 claims
- 0571US7313776B2Method and apparatus for routing an integrated circuitSYNOPSYS INC·Filed 2005·Granted Dec 25, 2007·8 cites·18 claims
- 0658US8001514B2Method and apparatus for computing a detailed routability estimationSYNOPSYS INC·Filed 2008·Granted Aug 16, 2011·2 cites·25 claims
- 0755US11694016B2Fast topology bus router for interconnect planningSYNOPSYS INC·Filed 2021·Granted Jul 4, 2023·0 cites·17 claims
- 0846US12073156B2Propagating physical design information through logical design hierarchy of an electronic circuitSYNOPSYS INC·Filed 2022·Granted Aug 27, 2024·0 cites·20 claims
- 0944US9026974B2Semiconductor integrated circuit partitioning and timingSYNOPSYS INC·Filed 2013·Granted May 5, 2015·0 cites·18 claims
- 1042US10372860B2Netlist abstraction for circuit design floorplanningSYNOPSYS INC·Filed 2015·Granted Aug 6, 2019·0 cites·18 claims
- 1138US10318692B2Scalable chip placementSYNOPSYS INC·Filed 2015·Granted Jun 11, 2019·0 cites·15 claims
- 1233US9747403B2Power-and-ground (PG) network characterization and distributed PG network creation for hierarchical circuit designsSYNOPSYS INC·Filed 2015·Granted Aug 29, 2017·0 cites·15 claims
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