Inventor · disambiguated record
Vijayalakshmi Ranganna
Also filed as: RANGANNA VIJAYALAKSHMI
1 granted patent·4 pending applications·31 citations·filing 2011–2015
44Inventor score
Files withQUALCOMM INC5
Top patents by PatentIndex Score
5 records- 0191US9070552B1Adaptive standard cell architecture and layout techniques for low area digital SoCQUALCOMM INC·Filed 2014·Granted Jun 30, 2015·31 cites·27 claims
- 0238US2015287709A1Double patterned stacking techniqueQUALCOMM INC·Filed 2014·Application pending·0 cites
- 0333US2013032885A1Area efficient gridded polysilicon layoutsQUALCOMM INC·Filed 2011·Application pending·0 cites
- 0428US2015109025A1Area saving in latch arraysQUALCOMM INC·Filed 2013·Application pending·0 cites
- 0525US2016217227A1Adaptive low power and high performance logic design and physical design techniquesQUALCOMM INC·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →