Inventor · disambiguated record
Paul D. Madland
Also filed as: MADLAND PAUL · MADLAND PAUL D · MADLAND PAUL DALE
29 granted patents·1,502 citations·filing 1975–2004
98Inventor score
Top patents by PatentIndex Score
29 records- 0193US5018111ATiming circuit for memory employing reset functionINTEL CORP·Filed 1988·Granted May 21, 1991·79 cites·8 claims
- 0289US5526510AMethod and apparatus for implementing a single clock cycle line replacement in a data cache unitINTEL CORP·Filed 1994·Granted Jun 11, 1996·157 cites·12 claims
- 0388US5881262AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1997·Granted Mar 9, 1999·126 cites·45 claims
- 0488US5751983AOut-of-order processor with a memory subsystem which handles speculatively dispatched load operationsFiled 1995·Granted May 12, 1998·140 cites·26 claims
- 0586US7042259B2Adaptive frequency clock generation systemINTEL CORP·Filed 2004·Granted May 9, 2006·34 cites·30 claims
- 0685US5532636ASource-switched charge pump circuitINTEL CORP·Filed 1995·Granted Jul 2, 1996·64 cites·2 claims
- 0785US3986044AClocked IGFET voltage level sustaining circuitMOTOROLA INC·Filed 1975·Granted Oct 12, 1976·23 cites·1 claims
- 0881US5671444AMethods and apparatus for caching data in a non-blocking manner using a plurality of fill buffersINTEL CORPORAITON·Filed 1996·Granted Sep 23, 1997·104 cites·39 claims
- 0980US5724536AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1994·Granted Mar 3, 1998·74 cites·32 claims
- 1079US5606670AMethod and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer systemINTEL CORP·Filed 1996·Granted Feb 25, 1997·80 cites·32 claims
- 1177US5577200AMethod and apparatus for loading and storing misaligned data on an out-of-order execution computer systemINTEL CORP·Filed 1995·Granted Nov 19, 1996·80 cites·52 claims
- 1275US4926387AMemory timing circuit employing scaled-down models of bit lines using reduced number of memory cellsINTEL CORP·Filed 1988·Granted May 15, 1990·31 cites·10 claims
- 1370US5680572ACache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffersINTEL CORP·Filed 1996·Granted Oct 21, 1997·58 cites·28 claims
- 1468US6737880B2Device and method for probing instantaneous high-speed local supply voltage fluctuation in VLSI integrated circuits using IR emissionsINTEL CORP·Filed 2001·Granted May 18, 2004·13 cites·18 claims
- 1567US7282975B2Apparatus and method to control self-timed and synchronous systemsINTEL CORP·Filed 2003·Granted Oct 16, 2007·11 cites·30 claims
- 1666US5748937AComputer system that maintains processor ordering consistency by snooping an external bus for conflicts during out of order execution of memory access instructionsINTEL CORP·Filed 1997·Granted May 5, 1998·47 cites·17 claims
- 1765US5826109AMethod and apparatus for performing multiple load operations to the same memory location in a computer systemINTEL CORP·Filed 1996·Granted Oct 20, 1998·49 cites·18 claims
- 1865US5694574AMethod and apparatus for performing load operations in a computer systemINTEL CORP·Filed 1996·Granted Dec 2, 1997·48 cites·53 claims
- 1965US5664137AMethod and apparatus for executing and dispatching store operations in a computer systemINTEL CORP·Filed 1995·Granted Sep 2, 1997·52 cites·49 claims
- 2062US5588126AMethods and apparatus for fordwarding buffered store data on an out-of-order execution computer systemINTEL CORP·Filed 1995·Granted Dec 24, 1996·36 cites·8 claims
- 2161US5860154AMethod and apparatus for calculating effective memory addressesINTEL CORP·Filed 1997·Granted Jan 12, 1999·39 cites·14 claims
- 2260US5717882AMethod and apparatus for dispatching and executing a load operation to memoryINTEL CORP·Filed 1996·Granted Feb 10, 1998·37 cites·34 claims
- 2359US5434987AMethod and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered storeINTEL CORP·Filed 1994·Granted Jul 18, 1995·33 cites·24 claims
- 2459US5031141AApparatus for generating self-timing for on-chip cacheINTEL CORP·Filed 1990·Granted Jul 9, 1991·34 cites·13 claims
- 2557US6378062B1Method and apparatus for performing a store operationINTEL CORP·Filed 1997·Granted Apr 23, 2002·32 cites·63 claims
- 2653US6573755B2Symmetric differential domino “AND gate”INTEL CORP·Filed 2001·Granted Jun 3, 2003·6 cites·32 claims
- 2750US4727518AApparatus for limiting minority carrier injection in CMOS memoriesINTEL CORP·Filed 1984·Granted Feb 23, 1988·7 cites·14 claims
- 2847US6377078B1Circuit to reduce charge sharing for domino circuits with pulsed clocksINTEL CORP·Filed 1999·Granted Apr 23, 2002·8 cites·46 claims
- 2930US5844852AMemory arrays with integrated bit line voltage stabilization circuitryINTEL CORP·Filed 1997·Granted Dec 1, 1998·0 cites·18 claims
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