Inventor · disambiguated record
Soren T. Soe
Also filed as: SOE SOREN · SOE SOREN T
15 granted patents·1 pending application·460 citations·filing 1994–2022
93Inventor score
Files withXILINX INC16
Top patents by PatentIndex Score
16 records- 0194US10402223B1Scheduling hardware resources for offloading functions in a heterogeneous computing systemXILINX INC·Filed 2017·Granted Sep 3, 2019·14 cites·20 claims
- 0293US7129747B1CPLD with fast logic sharing between function blocksXILINX INC·Filed 2004·Granted Oct 31, 2006·58 cites·18 claims
- 0392US5963048AMethod for programming complex PLD having more than one function block typeXILINX INC·Filed 1997·Granted Oct 5, 1999·183 cites·20 claims
- 0489US11163605B1Heterogeneous execution pipeline across different processor architectures and FPGA fabricXILINX INC·Filed 2019·Granted Nov 2, 2021·8 cites·18 claims
- 0589US10956241B1Unified container for hardware and software binariesXILINX INC·Filed 2017·Granted Mar 23, 2021·7 cites·10 claims
- 0687US11086815B1Supporting access to accelerators on a programmable integrated circuit by multiple host processesXILINX INC·Filed 2019·Granted Aug 10, 2021·6 cites·20 claims
- 0786US5636368AMethod for programming complex PLD having more than one function block typeXILINX INC·Filed 1994·Granted Jun 3, 1997·109 cites·22 claims
- 0884US7620929B1Programmable logic device having a programmable selector circuitXILINX INC·Filed 2008·Granted Nov 17, 2009·12 cites·9 claims
- 0977US7345508B1Programmable logic device having a programmable selector circuitXILINX INC·Filed 2006·Granted Mar 18, 2008·8 cites·16 claims
- 1077US6484292B1Incremental logic synthesis system for revisions of logic circuit designsXILINX INC·Filed 2000·Granted Nov 19, 2002·28 cites·16 claims
- 1166US10877766B2Embedded scheduling of hardware resources for hardware accelerationXILINX INC·Filed 2018·Granted Dec 29, 2020·1 cites·16 claims
- 1262US11720422B1Unified container for hardware and software binariesXILINX INC·Filed 2021·Granted Aug 8, 2023·0 cites·18 claims
- 1353US6336211B1Method and apparatus for implementing type-safe heterogeneous property listsXILINX INC·Filed 1999·Granted Jan 1, 2002·26 cites·18 claims
- 1448US2024211302A1Dynamic provisioning of portions of a data processing array for spatial and temporal sharingXILINX INC·Filed 2022·Application pending·0 cites
- 1547US11694066B2Machine learning runtime library for neural network accelerationXILINX INC·Filed 2017·Granted Jul 4, 2023·0 cites·20 claims
- 1644US10705993B2Programming and controlling compute units in an integrated circuitXILINX INC·Filed 2018·Granted Jul 7, 2020·0 cites·19 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →