Inventor · disambiguated record
Sanjay Deshpande
Also filed as: DESHPANDE SANJAY · DESHPANDE SANJAY R · DESHPANDE SANJAY RAGHUNATH
50 granted patents·6 pending applications·1,163 citations·filing 1994–2024
98Inventor score
Top patents by PatentIndex Score
56 records- 0197US11477005B1Systems for multi-blockchain, multi-token interoperability via common blockchain integration and methods of use thereofTASSAT GROUP INC·Filed 2022·Granted Oct 18, 2022·17 cites·20 claims
- 0296US11797365B1Computerized systems and methods for configuration of network interfaces of a distributed networkTASSAT GROUP INC·Filed 2022·Granted Oct 24, 2023·7 cites·20 claims
- 0396US11606188B1Systems for multi-blockchain, multi-token interoperability via common blockchain integrationTASSAT GROUP INC·Filed 2022·Granted Mar 14, 2023·8 cites·18 claims
- 0492US11882205B2Systems for multi-blockchain, multi-token interoperability via common blockchain integrationTASSAT GROUP INC·Filed 2023·Granted Jan 23, 2024·2 cites·20 claims
- 0591US6381362B1Method and apparatus for including virtual ads in video presentationsTATA AMERICA INTERNAT CORP·Filed 1999·Granted Apr 30, 2002·234 cites·15 claims
- 0690US7158666B2Method and apparatus for including virtual ads in video presentationsTATA AMERICA INTERNAT CORP·Filed 2001·Granted Jan 2, 2007·62 cites·4 claims
- 0785US10114748B2Distributed reservation based coherency protocolFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Oct 30, 2018·4 cites·20 claims
- 0883US11895252B2Method, controller, and computer-readable medium for network addressing on a distributed crypto ledger networkTASSAT GROUP INC·Filed 2022·Granted Feb 6, 2024·1 cites·21 claims
- 0983US6606676B1Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor systemIBM·Filed 1999·Granted Aug 12, 2003·105 cites·20 claims
- 1081US6317811B1Method and system for reissuing load requests in a multi-stream prefetch designIBM·Filed 1999·Granted Nov 13, 2001·95 cites·25 claims
- 1177US7949869B2Establishing relative identityREL ID TECHNOLOGIES INC·Filed 2010·Granted May 24, 2011·9 cites·15 claims
- 1275US12192317B2Systems for multi-blockchain, multi-token interoperability via common blockchain integrationTASSAT GROUP INC·Filed 2023·Granted Jan 7, 2025·0 cites·23 claims
- 1372US11546131B1Method, controller, and computer-readable medium for network addressing on a distributed crypto ledger networkTASSAT GROUP INC·Filed 2022·Granted Jan 3, 2023·0 cites·21 claims
- 1472US7941499B2Interprocessor message transmission via coherency-based interconnectFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 10, 2011·6 cites·20 claims
- 1572US6779036B1Method and apparatus for achieving correct order among bus memory transactions in a physically distributed SMP systemIBM·Filed 1999·Granted Aug 17, 2004·60 cites·7 claims
- 1671US12242904B2Computerized systems and methods for configuration of network interfaces of a distributed networkTASSAT GROUP INC·Filed 2023·Granted Mar 4, 2025·0 cites·19 claims
- 1771US6725307B1Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor systemIBM·Filed 1999·Granted Apr 20, 2004·59 cites·16 claims
- 1870US6467012B1Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessorsIBM·Filed 1999·Granted Oct 15, 2002·59 cites·28 claims
- 1969US7949867B2Secure communicationsREL ID TECHNOLOGIES INC·Filed 2006·Granted May 24, 2011·5 cites·10 claims
- 2068US9448741B2Piggy-back snoops for non-coherent memory transactions within distributed processing systemsDESHPANDE SANJAY R·Filed 2014·Granted Sep 20, 2016·2 cites·20 claims
- 2168US5781757AAdaptive scalable cache coherence network for a multiprocessor data processing systemIBM·Filed 1996·Granted Jul 14, 1998·55 cites·7 claims
- 2266US10628329B2Data processing system having a coherency interconnectFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Apr 21, 2020·1 cites·18 claims
- 2364US8554967B2Flow control mechanisms for avoidance of retries and/or deadlocks in an interconnectDESHPANDE SANJAY·Filed 2009·Granted Oct 8, 2013·3 cites·24 claims
- 2464US8473644B2Access management technique with operation translation capabilityDESHPANDE SANJAY·Filed 2009·Granted Jun 25, 2013·3 cites·18 claims
- 2564US6484220B1Transfer of data between processors in a multi-processor systemIBM·Filed 1999·Granted Nov 19, 2002·42 cites·35 claims
- 2664US5673413AMethod and apparatus for coherency reporting in a multiprocessing systemIBM·Filed 1995·Granted Sep 30, 1997·43 cites·22 claims
- 2763US12411761B1Fully cache coherent virtual partitions in multitenant configurations in a multiprocessor systemNVIDIA CORP·Filed 2024·Granted Sep 9, 2025·0 cites·20 claims
- 2863US9026742B2System and method for processing potentially self-inconsistent memory transactionsDESHPANDE SANJAY R·Filed 2007·Granted May 5, 2015·3 cites·20 claims
- 2963US8990633B2Tracing support for interconnect fabricXU ZHENG·Filed 2009·Granted Mar 24, 2015·2 cites·23 claims
- 3063US6449698B1Method and system for bypass prefetch data pathIBM·Filed 1999·Granted Sep 10, 2002·39 cites·17 claims
- 3162US9720847B2Least recently used (LRU) cache replacement implementation using a FIFO storing indications of whether a way of the cache was most recently accessedFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Aug 1, 2017·1 cites·18 claims
- 3262US6516379B1Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor systemIBM·Filed 1999·Granted Feb 4, 2003·38 cites·29 claims
- 3359US7502893B2System and method for reporting cache coherency state retained within a cache hierarchy of a processing nodeFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 10, 2009·1 cites·20 claims
- 3459US6591348B1Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor systemIBM·Filed 1999·Granted Jul 8, 2003·42 cites·25 claims
- 3559US6442597B1Providing global coherence in SMP systems using response combination block coupled to address switch connecting node controllers to memoryIBM·Filed 1999·Granted Aug 27, 2002·33 cites·16 claims
- 3659US5692135AMethod and system for performing an asymmetric bus arbitration protocol within a data processing systemIBM·Filed 1995·Granted Nov 25, 1997·41 cites·13 claims
- 3756US6434638B1Arbitration protocol for peer-to-peer communication in synchronous systemsIBM·Filed 1994·Granted Aug 13, 2002·28 cites·9 claims
- 3855US2003110106A1System and method for enabling content providers in a financial services organization to self-publish contentFiled 2001·Application pending·0 cites
- 3953US9977750B2Coherent memory interleaving with uniform latencyFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted May 22, 2018·0 cites·20 claims
- 4053US5717853AInformation handling system having router including first mode for configuring itself, second mode for configuring its connected devices and third mode for system operationIBM·Filed 1995·Granted Feb 10, 1998·27 cites·9 claims
- 4151US7529799B2Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor systemIBM·Filed 2002·Granted May 5, 2009·2 cites·21 claims
- 4250US9665518B2Methods and systems for controlling ordered write transactions to multiple devices using switch point networksDESHPANDE SANJAY R·Filed 2014·Granted May 30, 2017·0 cites·24 claims
- 4349US2010228943A1Access management technique for storage-efficient mapping between identifier domainsFREESCALE SEMICONDUCTOR INC·Filed 2009·Application pending·0 cites
- 4448US12010204B2Systems for multi-blockchain, multi-token interoperability via common blockchain integrationTASSAT GROUP INC·Filed 2022·Granted Jun 11, 2024·0 cites·21 claims
- 4546US2009019232A1Specification of coherence domain during address translationFREESCALE SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 4644US2003120874A1Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlockFiled 2003·Application pending·0 cites
- 4743US2009249445A1Authentication of Websites Based on Signature MatchingDESHPANDE SANJAY·Filed 2008·Application pending·0 cites
- 4842US10346089B2Data processing system having a write request network and a write data networkFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Jul 9, 2019·0 cites·15 claims
- 4942US2025119298A1System and method for quantum safe trust identity and authenticationFORTYTWO42 LABS LLP·Filed 2024·Application pending·0 cites
- 5040US9632933B2Efficient coherency response mechanismFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Apr 25, 2017·0 cites·17 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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