Inventor · disambiguated record
Erik M. Dahlstrom
Also filed as: DAHLSTROM ERIK M · DAHLSTROM ERIK MATTIAS
12 granted patents·1 pending application·31 citations·filing 2007–2013
88Inventor score
Top patents by PatentIndex Score
13 records- 0185US8598660B2Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltageCAMILLO-CASTILLO RENATA·Filed 2011·Granted Dec 3, 2013·7 cites·11 claims
- 0282US8710500B2Bipolar junction transistor with a self-aligned emitter and baseIBM·Filed 2013·Granted Apr 29, 2014·5 cites·16 claims
- 0378US8232156B2Vertical heterojunction bipolar transistors with reduced base-collector junction capacitanceCAMILLO-CASTILLO RENATA·Filed 2010·Granted Jul 31, 2012·4 cites·19 claims
- 0474US8586423B2Silicon controlled rectifier with stress-enhanced adjustable trigger voltageCAMILLO-CASTILLO RENATA·Filed 2011·Granted Nov 19, 2013·3 cites·16 claims
- 0574US8338863B2Vertical heterojunction bipolar transistors with reduced base-collector junction capacitanceCAMILLO-CASTILLO RENATA·Filed 2012·Granted Dec 25, 2012·3 cites·10 claims
- 0673US7696604B2Silicon germanium heterostructure barrier varactorIBM·Filed 2007·Granted Apr 13, 2010·4 cites·18 claims
- 0764US8946799B2Silicon controlled rectifier with stress-enhanced adjustable trigger voltageIBM·Filed 2013·Granted Feb 3, 2015·1 cites·18 claims
- 0863US9034712B2Stress enhanced LDMOS transistor to minimize on-resistance and maintain high breakdown voltageIBM·Filed 2013·Granted May 19, 2015·1 cites·11 claims
- 0962US8163612B2Silicon germanium heterostructure barrier varactorDAHLSTROM ERIK M·Filed 2009·Granted Apr 24, 2012·2 cites·20 claims
- 1059US8389372B2Heterojunction bipolar transistors with reduced base resistanceDAHLSTROM ERIK M·Filed 2010·Granted Mar 5, 2013·1 cites·11 claims
- 1151US8513706B2Heterojunction bipolar transistors with reduced base resistanceIBM·Filed 2012·Granted Aug 20, 2013·0 cites·20 claims
- 1248US8492237B2Methods of fabricating a bipolar junction transistor with a self-aligned emitter and baseCHAN KEVIN K·Filed 2011·Granted Jul 23, 2013·0 cites·19 claims
- 1337US2008204068A1Method for estimating defects in an npn transistor arrayIBM·Filed 2007·Application pending·0 cites
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