Inventor · disambiguated record
D. Michael Bell
Also filed as: BELL D M · BELL D MICHAEL
23 granted patents·1 pending application·1,384 citations·filing 1993–2005
97Inventor score
Top patents by PatentIndex Score
24 records- 0194US5546546AMethod and apparatus for maintaining transaction ordering and arbitrating in a bus bridgeINTEL CORP·Filed 1994·Granted Aug 13, 1996·181 cites·28 claims
- 0290US5905876AQueue ordering for memory and I/O transactions in a multiple concurrent transaction computer systemINTEL CORP·Filed 1996·Granted May 18, 1999·163 cites·15 claims
- 0389US5434996ASynchronous/asynchronous clock net with autosenseINTEL CORP·Filed 1993·Granted Jul 18, 1995·99 cites·34 claims
- 0486US6317799B1Destination controlled remote DMA engineINTEL CORP·Filed 2000·Granted Nov 13, 2001·37 cites·25 claims
- 0586US6070207AHot plug connected I/O bus for computer systemINTEL CORP·Filed 1998·Granted May 30, 2000·119 cites·20 claims
- 0686US6021451AMethod and apparatus for maintaining transaction ordering and arbitrating in a bus bridgeINTEL CORP·Filed 1998·Granted Feb 1, 2000·102 cites·32 claims
- 0786US5535340AMethod and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridgeINTEL CORP·Filed 1994·Granted Jul 9, 1996·122 cites·37 claims
- 0883US5410707ABootstrap loading from external memory including disabling a reset from a keyboard controller while an operating system load signal is activeINTEL CORP·Filed 1994·Granted Apr 25, 1995·99 cites·17 claims
- 0981US5594882APCI split transactions utilizing dual address cycleINTEL CORP·Filed 1995·Granted Jan 14, 1997·98 cites·11 claims
- 1079US7480747B2Method and apparatus to reduce latency and improve throughput of input/output data in a processorINTEL CORP·Filed 2005·Granted Jan 20, 2009·9 cites·20 claims
- 1172US5835739AMethod and apparatus for maintaining transaction ordering and arbitrating in a bus bridgeINTEL CORP·Filed 1997·Granted Nov 10, 1998·49 cites·28 claims
- 1270US6081851AMethod and apparatus for programming a remote DMA engine residing on a first bus from a destination residing on a second busINTEL CORP·Filed 1997·Granted Jun 27, 2000·47 cites·41 claims
- 1369US7535918B2Copy on access mechanisms for low latency data movementINTEL CORP·Filed 2005·Granted May 19, 2009·4 cites·20 claims
- 1467US6330630B1Computer system having improved data transfer across a bus bridgeINTEL CORP·Filed 1999·Granted Dec 11, 2001·49 cites·26 claims
- 1567US6108736ASystem and method of flow control for a high speed busINTEL CORP·Filed 1997·Granted Aug 22, 2000·49 cites·41 claims
- 1664US5828865ADual mode bus bridge for interfacing a host bus and a personal computer interface busINTEL CORP·Filed 1995·Granted Oct 27, 1998·38 cites·10 claims
- 1760US6148356AScalable computer systemINTEL CORP·Filed 1998·Granted Nov 14, 2000·43 cites·15 claims
- 1858US6266778B1Split transaction I/O bus with pre-specified timing protocols to synchronously transmit packets between devices over multiple cyclesINTEL CORP·Filed 1999·Granted Jul 24, 2001·24 cites·15 claims
- 1956US6047120ADual mode bus bridge for interfacing a host bus and a personal computer interface busINTEL CORP·Filed 1998·Granted Apr 4, 2000·26 cites·13 claims
- 2041US2007002853A1Snoop bandwidth reductionVASUDEVAN ANIL·Filed 2005·Application pending·0 cites
- 2137US6134622ADual mode bus bridge for computer systemINTEL CORP·Filed 1998·Granted Oct 17, 2000·12 cites·7 claims
- 2235US7107371B1Method and apparatus for providing and embedding control information in a bus systemINTEL CORP·Filed 1997·Granted Sep 12, 2006·7 cites·10 claims
- 2335US6088370AFast 16 bit, split transaction I/O busINTEL CORP·Filed 1997·Granted Jul 11, 2000·5 cites·11 claims
- 2432US7016989B1Fast 16 bit, split transaction I/O busINTEL CORP·Filed 1999·Granted Mar 21, 2006·2 cites·23 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →