Inventor · disambiguated record
Steven Lee Gregor
Also filed as: GREGOR STEVEN · GREGOR STEVEN L · GREGOR STEVEN LEE
44 granted patents·1,353 citations·filing 1988–2022
98Inventor score
Top patents by PatentIndex Score
44 records- 0196US5023776AStore queue for a tightly coupled multiple processor configuration with two-level cache buffer storageIBM·Filed 1988·Granted Jun 11, 1991·228 cites·15 claims
- 0294US7168005B2Programable multi-port memory BIST with compact microcodeCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jan 23, 2007·91 cites·41 claims
- 0392US10706952B1Testing for memories during mission mode self-testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jul 7, 2020·14 cites·20 claims
- 0492US6557127B1Method and apparatus for testing multi-port memoriesCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Apr 29, 2003·67 cites·18 claims
- 0590US9640280B1Power domain aware insertion methods and designs for testing and repairing memoryCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 2, 2017·8 cites·20 claims
- 0690US5276848AShared two level cache including apparatus for maintaining storage consistencyIBM·Filed 1991·Granted Jan 4, 1994·184 cites·1 claims
- 0789US10706950B1Testing for memory error correction code logicCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jul 7, 2020·10 cites·20 claims
- 0888US6161208AStorage subsystem including an error correcting cache and means for performing memory to memory transfersIBM·Filed 1999·Granted Dec 12, 2000·154 cites·2 claims
- 0987US9865362B1Method and apparatus for testing error correction code (ECC) logic and physical memory onboard a manufactured integrated circuit (IC)CADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 9, 2018·9 cites·20 claims
- 1087US6874111B1System initialization of microcode-based memory built-in self-testIBM·Filed 2000·Granted Mar 29, 2005·48 cites·15 claims
- 1184US10095822B1Memory built-in self-test logic in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Oct 9, 2018·4 cites·20 claims
- 1283US10192013B1Test logic at register transfer level in an integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jan 29, 2019·5 cites·20 claims
- 1383US8677196B1Low cost production testing for memoryGREGOR STEVEN LEE·Filed 2011·Granted Mar 18, 2014·14 cites·32 claims
- 1483US6651201B1Programmable memory built-in self-test combining microcode and finite state machine self-testIBM·Filed 2000·Granted Nov 18, 2003·36 cites·20 claims
- 1581US5553305ASystem for synchronizing execution by a processing element of threads within a process using a state indicatorIBM·Filed 1992·Granted Sep 3, 1996·93 cites·30 claims
- 1679US8719761B2Method and apparatus for optimizing memory-built-in-self testCARD NORMAN·Filed 2012·Granted May 6, 2014·8 cites·44 claims
- 1778US10783299B1Simulation event reduction and power control during MBIST through clock tree managementCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·2 cites·20 claims
- 1877US10387599B1Systems, methods, and computer-readable media utilizing improved data structures and design flow for programmable memory built-in self-test (PMBIST)CADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 20, 2019·2 cites·22 claims
- 1977US8296703B1Fault modeling for state retention logicCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Oct 23, 2012·9 cites·26 claims
- 2075US8271226B2Testing state retention logic in low power systemsCHAKRAVADHANULA KRISHNA·Filed 2008·Granted Sep 18, 2012·8 cites·23 claims
- 2175US6490660B1Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor systemIBM·Filed 2000·Granted Dec 3, 2002·19 cites·7 claims
- 2273US8990749B2Method and apparatus for optimizing memory-built-in-self testARORA PUNEET·Filed 2012·Granted Mar 24, 2015·4 cites·20 claims
- 2373US5860138AProcessor with compiler-allocated, variable length intermediate storageIBM·Filed 1995·Granted Jan 12, 1999·69 cites·37 claims
- 2472US10699795B1System, method and computer-accessible medium for automated identification of embedded physical memories using shared test bus access in intellectual property coresCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 30, 2020·1 cites·21 claims
- 2572US7003704B2Two-dimensional redundancy calculationIBM·Filed 2002·Granted Feb 21, 2006·20 cites·13 claims
- 2672US5450563AStorage protection keys in two level cache systemIBM·Filed 1992·Granted Sep 12, 1995·59 cites·18 claims
- 2769US10007489B1Automated method identifying physical memories within a core or macro integrated circuit designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jun 26, 2018·1 cites·15 claims
- 2869US4924466ADirect hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer systemIBM·Filed 1988·Granted May 8, 1990·37 cites·14 claims
- 2968US6115795AMethod and apparatus for configurable multiple level cache with coherency in a multiprocessor systemIBM·Filed 1997·Granted Sep 5, 2000·44 cites·9 claims
- 3067US10319459B1Customizable built-in self-test testplans for memory unitsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jun 11, 2019·2 cites·20 claims
- 3164US5909694AMultiway associative external microprocessor cacheIBM·Filed 1997·Granted Jun 1, 1999·42 cites·6 claims
- 3260US11971818B1Memory view for non-volatile memory moduleCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Apr 30, 2024·0 cites·20 claims
- 3360US6907554B2Built-in self test system and method for two-dimensional memory redundancy allocationIBM·Filed 2003·Granted Jun 14, 2005·11 cites·20 claims
- 3459US11966633B1Control algorithm generator for non-volatile memory moduleCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Apr 23, 2024·0 cites·20 claims
- 3558US10593419B1Failing read count diagnostics for memory built-in self-testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Mar 17, 2020·1 cites·15 claims
- 3657US12417029B1Memory view for memory moduleCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Sep 16, 2025·0 cites·20 claims
- 3754US10541043B1On demand data stream controller for programming and executing operations in an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Jan 21, 2020·1 cites·19 claims
- 3853US10395747B1Register-transfer level design engineering change order strategyCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 27, 2019·0 cites·22 claims
- 3953US5313613AExecution of storage-immediate and storage-storage instructions within cache buffer storageIBM·Filed 1993·Granted May 17, 1994·24 cites·6 claims
- 4051US5226169ASystem for execution of storage-immediate and storage-storage instructions within cache buffer storageIBM·Filed 1991·Granted Jul 6, 1993·23 cites·25 claims
- 4141US10504607B1Multiple-channel, programmable fuse control unitCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Dec 10, 2019·0 cites·23 claims
- 4241US10482989B1Dynamic diagnostics analysis for memory built-in self-testCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Nov 19, 2019·0 cites·20 claims
- 4338US7032144B2Method and apparatus for testing multi-port memoriesCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Apr 18, 2006·1 cites·12 claims
- 4436US10387598B1Verifying results in simulation through simulation add-on to support visualization of selected memory contents in real timeCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 20, 2019·0 cites·7 claims
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