Inventor · disambiguated record
Juergen Lahner
Also filed as: LAHNER JUERGEN · LAHNER JUERGEN K
17 granted patents·2 pending applications·319 citations·filing 2000–2009
94Inventor score
Top patents by PatentIndex Score
19 records- 0195US7895546B2Statistical design closureLSI CORP·Filed 2007·Granted Feb 22, 2011·100 cites·20 claims
- 0281US6546538B1Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak powerLSI LOGIC CORP·Filed 2000·Granted Apr 8, 2003·41 cites·13 claims
- 0380US7082584B2Automated analysis of RTL code containing ASIC vendor rulesLSI LOGIC CORP·Filed 2003·Granted Jul 25, 2006·40 cites·4 claims
- 0479US7441210B2On-the-fly RTL instructor for advanced DFT and design closureLSI CORP·Filed 2005·Granted Oct 21, 2008·10 cites·20 claims
- 0575US7415687B2Method and computer program for incremental placement and routing with nested shellsLSI CORP·Filed 2005·Granted Aug 19, 2008·8 cites·18 claims
- 0675US6990651B2Advanced design format library for integrated circuit design synthesis and floorplanning toolsLSI LOGIC CORP·Filed 2003·Granted Jan 24, 2006·23 cites·15 claims
- 0772US6532576B1Cell interconnect delay library for integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Mar 11, 2003·17 cites·16 claims
- 0871US7000163B1Optimized buffering for JTAG boundary scan netsLSI LOGIC CORP·Filed 2002·Granted Feb 14, 2006·17 cites·16 claims
- 0968US6438730B1RTL code optimization for resource sharing structuresLSI LOGIC CORP·Filed 2001·Granted Aug 20, 2002·20 cites·13 claims
- 1066US6766499B1Buffer cell insertion and electronic design automationLSI LOGIC CORP·Filed 2001·Granted Jul 20, 2004·11 cites·18 claims
- 1163US7844929B2Optimizing test code generation for verification environmentLSI CORP·Filed 2008·Granted Nov 30, 2010·4 cites·20 claims
- 1262US7412678B2Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit designLSI CORP·Filed 2004·Granted Aug 12, 2008·9 cites·16 claims
- 1361US7380228B2Method of associating timing violations with critical structures in an integrated circuit designLSI CORP·Filed 2004·Granted May 27, 2008·10 cites·14 claims
- 1459US7594201B2Enhanced method of optimizing multiplex structures and multiplex control structures in RTL codeLSI CORP·Filed 2006·Granted Sep 22, 2009·2 cites·28 claims
- 1553US6757885B1Length matrix generator for register transfer level codeLSI LOGIC CORP·Filed 2002·Granted Jun 29, 2004·4 cites·10 claims
- 1647US7086015B2Method of optimizing RTL code for multiplex structuresLSI LOGIC CORP·Filed 2004·Granted Aug 1, 2006·3 cites·6 claims
- 1746US2010217564A1Advanced physical simulatorLAHNER JUERGEN K·Filed 2009·Application pending·0 cites
- 1842US6907588B2Congestion estimation for register transfer level codeLSI LOGIC CORP·Filed 2002·Granted Jun 14, 2005·0 cites·14 claims
- 1939US2007079266A1Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design databaseLSI LOGIC CORP·Filed 2005·Application pending·0 cites
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