Inventor · disambiguated record
Victor A. Garibay
Also filed as: GARIBAY VICTOR · GARIBAY VICTOR A · GARIBAY VICTOR ANTHONY
10 granted patents·5 pending applications·43 citations·filing 2009–2019
85Inventor score
Files withIBM15
Top patents by PatentIndex Score
15 records- 0194US9726691B23D chip testing through micro-C4 interfaceIBM·Filed 2014·Granted Aug 8, 2017·24 cites·7 claims
- 0278US10832536B2Guided cable managementIBM·Filed 2018·Granted Nov 10, 2020·4 cites·20 claims
- 0377US10331605B2Dynamic re-allocation of signal lanesIBM·Filed 2016·Granted Jun 25, 2019·2 cites·17 claims
- 0474US10296484B2Dynamic re-allocation of computer bus lanesIBM·Filed 2015·Granted May 21, 2019·2 cites·20 claims
- 0573US10275362B2Dynamic address translation table allocationIBM·Filed 2018·Granted Apr 30, 2019·1 cites·14 claims
- 0672US8352702B2Data processing system memory allocationIBM·Filed 2009·Granted Jan 8, 2013·9 cites·18 claims
- 0768US10371717B23D chip testing through micro-C4 interfaceIBM·Filed 2017·Granted Aug 6, 2019·1 cites·6 claims
- 0858US11193953B23D chip testing through micro-C4 interfaceIBM·Filed 2019·Granted Dec 7, 2021·0 cites·2 claims
- 0958US10025725B2Dynamic address translation table allocationIBM·Filed 2017·Granted Jul 17, 2018·0 cites·14 claims
- 1056US2019243797A1Dynamic re-allocation of signal lanesIBM·Filed 2019·Application pending·0 cites
- 1148US2017177179A1E-reader summarization and customized dictionaryIBM·Filed 2016·Application pending·0 cites
- 1247US2017177178A1E-reader summarization and customized dictionaryIBM·Filed 2015·Application pending·0 cites
- 1339US10102074B2Switching allocation of computer bus lanesIBM·Filed 2015·Granted Oct 16, 2018·0 cites·17 claims
- 1437US2017154000A1Dynamic Re-Allocation of Computer Bus LanesIBM·Filed 2015·Application pending·0 cites
- 1537US2017153989A1Dynamic Allocation of Computer Bus LanesIBM·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →