Inventor · disambiguated record
Lyle Edwin Grosbach
Also filed as: GROSBACH LYLE E · GROSBACH LYLE EDWIN
11 granted patents·2 pending applications·111 citations·filing 1994–2012
88Inventor score
Top patents by PatentIndex Score
13 records- 0188US8856479B2Implementing storage adapter performance optimization with hardware operations completion coalescenceGERHARD ADRIAN C·Filed 2012·Granted Oct 7, 2014·18 cites·25 claims
- 0274US7660251B2Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidthIBM·Filed 2008·Granted Feb 9, 2010·5 cites·7 claims
- 0367US5751990AAbridged virtual address cache directoryIBM·Filed 1994·Granted May 12, 1998·48 cites·18 claims
- 0462US7362706B2Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidthIBM·Filed 2002·Granted Apr 22, 2008·7 cites·4 claims
- 0554US6000011AMulti-entry fully associative transition cacheIBM·Filed 1996·Granted Dec 7, 1999·29 cites·33 claims
- 0651US7567137B2Programmable oscillators for high frequency clock generation for simulation environmentsIBM·Filed 2007·Granted Jul 28, 2009·0 cites·8 claims
- 0748US7319367B2Programmable oscillators for high frequency clock generation for simulation environmentsIBM·Filed 2006·Granted Jan 15, 2008·0 cites·6 claims
- 0845US7475159B2High-speed schedulerIBM·Filed 2003·Granted Jan 6, 2009·0 cites·8 claims
- 0945US2005071503A1Hierarchical schedulingIBM·Filed 2003·Application pending·0 cites
- 1042US2007136699A1Dependency matrices and methods of using the same for testing or analyzing an integrated circuitIBM·Filed 2005·Application pending·0 cites
- 1130US6523080B1Shared bus non-sequential data ordering method and apparatusIBM·Filed 1998·Granted Feb 18, 2003·2 cites·6 claims
- 1229US5748919AShared bus non-sequential data ordering method and apparatusIBM·Filed 1996·Granted May 5, 1998·1 cites·3 claims
- 1328US5649177AControl logic for very fast clock speedsIBM·Filed 1995·Granted Jul 15, 1997·1 cites·21 claims
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