Inventor · disambiguated record
Timothy W. Budell
Also filed as: BUDELL TIMOTHY W
20 granted patents·3 pending applications·132 citations·filing 2002–2014
94Inventor score
Top patents by PatentIndex Score
23 records- 0180US8312404B2Multi-segments modeling bond wire interconnects with 2D simulations in high speed, high density wire bond packagesHU HAITIAN·Filed 2009·Granted Nov 13, 2012·12 cites·22 claims
- 0279US8952503B2Organic module EMI shielding structures and methodsIBM·Filed 2013·Granted Feb 10, 2015·4 cites·8 claims
- 0375US6793500B1Radial contact pad footprint and wiring for electrical componentsIBM·Filed 2003·Granted Sep 21, 2004·20 cites·17 claims
- 0473US7275229B2Auto connection assignment system and methodIBM·Filed 2005·Granted Sep 25, 2007·7 cites·24 claims
- 0571US7882469B2Automatic verification of adequate conductive return-current pathsIBM·Filed 2007·Granted Feb 1, 2011·5 cites·5 claims
- 0669US6978214B2Validation of electrical performance of an electronic package prior to fabricationIBM·Filed 2003·Granted Dec 20, 2005·12 cites·17 claims
- 0767US6762367B2Electronic package having high density signal wires with low resistanceIBM·Filed 2002·Granted Jul 13, 2004·13 cites·26 claims
- 0865US7351917B2Vents with signal image for signal return pathIBM·Filed 2005·Granted Apr 1, 2008·2 cites·17 claims
- 0964US9245854B2Organic module EMI shielding structures and methodsIBM·Filed 2014·Granted Jan 26, 2016·1 cites·18 claims
- 1063US7765509B2Auto connection assignment system and methodIBM·Filed 2007·Granted Jul 27, 2010·3 cites·20 claims
- 1163US7454723B2Validation of electrical performance of an electronic package prior to fabricationIBM·Filed 2005·Granted Nov 18, 2008·2 cites·11 claims
- 1262US7197446B2Hierarchical method of power supply noise and signal integrity analysisIBM·Filed 2004·Granted Mar 27, 2007·9 cites·30 claims
- 1360US7017128B2Concurrent electrical signal wiring optimization for an electronic packageIBM·Filed 2003·Granted Mar 21, 2006·8 cites·9 claims
- 1460US6703706B2Concurrent electrical signal wiring optimization for an electronic packageIBM·Filed 2002·Granted Mar 9, 2004·8 cites·17 claims
- 1559US7146596B2Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring gridIBM·Filed 2003·Granted Dec 5, 2006·10 cites·17 claims
- 1658US8429590B2System-level method for reducing power supply noise in an electronic systemBUDELL TIMOTHY W·Filed 2011·Granted Apr 23, 2013·1 cites·18 claims
- 1758US6977345B2Vents with signal image for signal return pathIBM·Filed 2002·Granted Dec 20, 2005·6 cites·11 claims
- 1858US6945791B2Integrated circuit redistribution packageIBM·Filed 2004·Granted Sep 20, 2005·8 cites·15 claims
- 1949US2008127485A1Vents with signal image for signal return pathBUDELL TIMOTHY W·Filed 2008·Application pending·0 cites
- 2042US8108811B2Validation of electrical performance of an electronic package prior to fabricationBUDELL TIMOTHY W·Filed 2008·Granted Jan 31, 2012·1 cites·20 claims
- 2142US2009094564A1Method for rapid return path tracingBUDELL TIMOTHY W·Filed 2007·Application pending·0 cites
- 2240US7196908B2Dual pitch contact pad footprint for flip-chip chips and modulesIBM·Filed 2003·Granted Mar 27, 2007·0 cites·20 claims
- 2334US2012074559A1Integrated circuit package using through substrate vias to ground lidBUDELL TIMOTHY W·Filed 2010·Application pending·0 cites
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