Inventor · disambiguated record
Gary B. Bronner
Also filed as: BRONNER GARY · BRONNER GARY B · BRONNER GARY BELA
128 granted patents·8 pending applications·3,812 citations·filing 1990–2024
99Inventor score
Top patents by PatentIndex Score
136 records- 0199US7470570B2Process for fabrication of FinFETsIBM·Filed 2006·Granted Dec 30, 2008·138 cites·14 claims
- 0298US8344475B2Integrated circuit heating to effect in-situ annealingRAMBUS INC·Filed 2010·Granted Jan 1, 2013·50 cites·38 claims
- 0398US6566177B1Silicon-on-insulator vertical array device trench capacitor DRAMIBM·Filed 1999·Granted May 20, 2003·279 cites·9 claims
- 0498US5606188AFabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memoryIBM·Filed 1995·Granted Feb 25, 1997·253 cites·13 claims
- 0596US11468947B2Techniques for initializing resistive memory devices by applying voltages with different polaritiesHEFEI RELIANCE MEMORY LTD·Filed 2020·Granted Oct 11, 2022·4 cites·11 claims
- 0695US11653580B2Non-volatile memory structure with positioned dopingHEFEI RELIANCE MEMORY LTD·Filed 2021·Granted May 16, 2023·2 cites·17 claims
- 0795US10037801B22T-1R architecture for resistive RAMHEFEI RELIANCE MEMORY LTD·Filed 2014·Granted Jul 31, 2018·14 cites·15 claims
- 0895US9305644B2Resistance memory cellKELLAM MARK D·Filed 2012·Granted Apr 5, 2016·20 cites·20 claims
- 0995US9230641B2Fast read speed memory deviceRAMBUS INC·Filed 2014·Granted Jan 5, 2016·12 cites·17 claims
- 1095US9202572B2Thermal anneal using word-line heating elementRAMBUS INC·Filed 2013·Granted Dec 1, 2015·13 cites·12 claims
- 1195US7129130B2Out of the box vertical transistor for eDRAM on SOIIBM·Filed 2005·Granted Oct 31, 2006·25 cites·10 claims
- 1295US5945707ADRAM cell with grooved transfer deviceIBM·Filed 1998·Granted Aug 31, 1999·127 cites·15 claims
- 1395US5360758ASelf-aligned buried strap for trench type DRAM cellsIBM·Filed 1993·Granted Nov 1, 1994·109 cites·7 claims
- 1494US9934851B2Resistance memory cellRAMBUS INC·Filed 2016·Granted Apr 3, 2018·11 cites·20 claims
- 1594US8716780B2Three-dimensional memory array stacking structureKELLAM MARK D·Filed 2010·Granted May 6, 2014·25 cites·34 claims
- 1694US6573137B1Single sided buried strapINFINEON TECHNOLOGIES CORP·Filed 2000·Granted Jun 3, 2003·58 cites·12 claims
- 1794US5362663AMethod of forming double well substrate plate trench DRAM cell arrayIBM·Filed 1993·Granted Nov 8, 1994·93 cites·6 claims
- 1893US10199098B22T-1R architecture for resistive RAMHEFEI RELIANCE MEMORY LTD·Filed 2018·Granted Feb 5, 2019·9 cites·7 claims
- 1993US6426526B1Single sided buried strapIBM·Filed 2001·Granted Jul 30, 2002·53 cites·6 claims
- 2093US6388294B1Integrated circuit using damascene gate structureIBM·Filed 2000·Granted May 14, 2002·69 cites·10 claims
- 2193US6242770B1Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the sameFiled 1998·Granted Jun 5, 2001·79 cites·24 claims
- 2292US6426252B1Silicon-on-insulator vertical array DRAM cell with self-aligned buried strapIBM·Filed 1999·Granted Jul 30, 2002·95 cites·29 claims
- 2392US6037194AMethod for making a DRAM cell with grooved transfer deviceIBM·Filed 1999·Granted Mar 14, 2000·82 cites·35 claims
- 2492US5508219ASOI DRAM with field-shield isolation and body contactIBM·Filed 1995·Granted Apr 16, 1996·108 cites·16 claims
- 2591US6348374B1Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structureIBM·Filed 2000·Granted Feb 19, 2002·45 cites·11 claims
- 2691US6087225AMethod for dual gate oxide dual workfunction CMOSIBM·Filed 1998·Granted Jul 11, 2000·92 cites·10 claims
- 2791US5876788AHigh dielectric TiO2 -SiN composite films for memory applicationsIBM·Filed 1997·Granted Mar 2, 1999·97 cites·31 claims
- 2890US8193573B2Repairing defects in a nonvolatile semiconductor memory device utilizing a heating elementBRONNER GARY B·Filed 2008·Granted Jun 5, 2012·23 cites·29 claims
- 2990US6767789B1Method for interconnection between transfer devices and storage capacitors in memory cells and device formed therebyIBM·Filed 1998·Granted Jul 27, 2004·106 cites·29 claims
- 3090US6727141B1DRAM having offset vertical transistors and methodIBM·Filed 2003·Granted Apr 27, 2004·42 cites·12 claims
- 3189US11651820B2Fast read speed memory deviceHEFEI RELIANCE MEMORY LTD·Filed 2022·Granted May 16, 2023·1 cites·18 claims
- 3289US9177655B2Pulse control for nonvolatile memoryRAMBUS INC·Filed 2014·Granted Nov 3, 2015·10 cites·21 claims
- 3388US10622062B22T-1R architecture for resistive ramHEFEI RELIANCE MEMORY LTD·Filed 2018·Granted Apr 14, 2020·5 cites·20 claims
- 3487US10388375B2Fast read speed memory deviceHEFEI RELIANCE MEMORY LTD·Filed 2018·Granted Aug 20, 2019·4 cites·15 claims
- 3587US5792703ASelf-aligned contact wiring process for SI devicesIBM·Filed 1996·Granted Aug 11, 1998·92 cites·24 claims
- 3687US5128271AHigh performance vertical bipolar transistor structure via self-aligning processing techniquesIBM·Filed 1990·Granted Jul 7, 1992·71 cites·30 claims
- 3786US7737502B2Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drainIBM·Filed 2006·Granted Jun 15, 2010·12 cites·10 claims
- 3886US6403423B1Modified gate processing for optimized definition of array and logic devices on same chipIBM·Filed 2000·Granted Jun 11, 2002·38 cites·30 claims
- 3985US9941005B2Fast read speed memory deviceRAMBUS INC·Filed 2016·Granted Apr 10, 2018·4 cites·15 claims
- 4085US9490009B2Fast read speed memory deviceRAMBUS INC·Filed 2016·Granted Nov 8, 2016·4 cites·20 claims
- 4185US7009237B2Out of the box vertical transistor for eDRAM on SOIIBM·Filed 2004·Granted Mar 7, 2006·23 cites·10 claims
- 4285US6429474B1Storage-capacitor electrode and interconnectIBM·Filed 2000·Granted Aug 6, 2002·35 cites·23 claims
- 4385US6281064B1Method for providing dual work function doping and protective insulating capIBM·Filed 1999·Granted Aug 28, 2001·61 cites·35 claims
- 4485US5250829ADouble well substrate plate trench DRAM cell arrayIBM·Filed 1992·Granted Oct 5, 1993·47 cites·5 claims
- 4584US11963465B2Non-volatile memory structure with positioned dopingHEFEI RELIANCE MEMORY LTD·Filed 2023·Granted Apr 16, 2024·0 cites·18 claims
- 4684US7759188B2Method of fabricating vertical body-contacted SOI transistorIBM·Filed 2007·Granted Jul 20, 2010·9 cites·8 claims
- 4784US6570208B26F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STIIBM·Filed 2001·Granted May 27, 2003·29 cites·11 claims
- 4884US2024224821A1Non-volatile memory structure with positioned dopingHEFEI RELIANCE MEMORY LTD·Filed 2024·Application pending·0 cites
- 4983US11018295B2Non-volatile memory structure with positioned dopingHEFEI RELIANCE MEMORY LTD·Filed 2017·Granted May 25, 2021·4 cites·18 claims
- 5083US10943655B2Techniques for initializing resistive memory devices by applying different polarity voltages across resistance change materialHEFEI RELIANCE MEMORY LTD·Filed 2017·Granted Mar 9, 2021·4 cites·25 claims
Showing the top 50 of 136 patent records by PatentIndex Score.
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