Inventor

LESEA AUSTIN H

US103 patents

⚠️ This page may combine multiple inventors who share the name “LESEA AUSTIN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LESEA AUSTIN H

XILINX INC

Supporting multiple FPGA configuration modes using dedicated on-chip processor

Realizing analog-to-digital converter on a digital programmable integrated circuit

Unique identifier derived from an intrinsic characteristic of an integrated circuit

Method and apparatus for detecting sudden temperature/voltage changes in integrated circuits

Method of correcting errors stored in a memory array

Method and apparatus for generating a phase locked spread spectrum clock signal

FPGA configuration memory with built-in error correction mechanism

Tunable clock distribution system for reducing power dissipation

Integrated testing of serializer/deserializer in FPGA

Phase-locked loop employing programmable tapped-delay-line oscillator

Bi-directional interface and communication link

Phase-locked loop employing programmable tapped-delay-line oscillator

Method and apparatus using a semiconductor die integrated antenna structure

Architecture for silicon photonics enabling wafer probe and test

Circuit for and method of routing data between die of an integrated circuit

Secure voltage regulator

Defense against attacks on ring oscillator-based physically unclonable functions

Method and apparatus for preventing accelerated aging of a physically unclonable function

Method for detecting and compensating for temperature effects

Determining voltage level validity for a power-on reset condition

FPGA with time-multiplexed interconnect

Configurable voltage bias circuit for controlling buffer delays

Control of simultaneous switch noise from multiple outputs

Memory cells enhanced for resistance to single event upset

Methods of utilizing noise cores in PLD designs to facilitate future design modifications

Method and circuit for glitchless clock control

Asymmetric bidirectional bus implemented using an I/O device with a digitally controlled impedance

Memory cells enhanced for resistance to single event upset

Method and structure for shipping a die as multiple products

Method and apparatus for adjusting delay in a delay locked loop for temperature variations

Programmable logic device having amplitude and phase modulation communication

Realizing analog-to-digital converter on a digital programmable integrated circuit

Circuit for and method of implementing a plurality of circuits on a programmable logic device

Method of measuring the performance of a transceiver in a programmable logic device

Low jitter digital frequency synthesizer and control thereof

System and method for storing a charging algorithm and charging methodology associated with a battery and selectively connecting a critical circuit to a battery voltage pin

Lateral cooling for multi-chip packages

Electro-absorption modulation with an integrated photodetector

Integrated circuit package having voltage regulation circuitry

Internal voltage monitoring for integrated circuit devices

Dynamic voltage scaling in programmable integrated circuits

LESEA AUSTIN H

Method of and circuit for correcting adjacent bit errors in a memory

Method and integrated circuit for secure encryption and decryption

Method and integrated circuit for secure encryption and decryption

Single-event-upset resistant memory cell with triple well

Duplicate design flow for mitigation of soft errors in IC operation

Method and apparatus for error upset detection and correction

ABUGHARBIEH KHALDOON S

Skew compensation for a stacked die

DURANGO SYSTEMS INC

Telephone call diverting and answering system

JAMES-ROXBY PHILIP B

Redundantly validating values with a processor and a check circuit