Inventor

HALBERT JOHN B

US80 patents

⚠️ This page may combine multiple inventors who share the name “HALBERT JOHN B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HALBERT JOHN B

INTEL CORP

Row hammer monitoring based on stored row hammer threshold value

Row hammer monitoring based on stored row hammer threshold value

Dual-port buffer-to-memory interface

Memory module having buffer for isolating stacked memory devices

Dual-port buffer-to-memory interface

Multi-tier point-to-point ring memory interface

Buffer to multiply memory interface

Multi-tier point-to-point buffered memory interface

Memory module having buffer for isolating stacked memory devices

Row hammer refresh command

Row hammer monitoring based on stored row hammer threshold value

Row hammer refresh command

Row hammer refresh command

Distributed row hammer tracking

Method, apparatus and system for responding to a row hammer event

Method and apparatus to counter mismatched burst lengths

Digital system of adjusting delays on circuit boards

Buffering data transfer between a chipset and memory modules

Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing

Memory interface having source-synchronous command/address signaling

Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules

Memory device having error checking and correction

Buffering and interleaving data transfer between a chipset and memory modules

Method and apparatus for providing debug functionality in a buffered memory channel

Memory device error check and scrub mode and error transparency

Memory device error check and scrub mode and error transparency

Memory device check bit read mode

Memory device on-die error checking and correcting code

Method, apparatus and system for responding to a row hammer event

Row hammer monitoring based on stored row hammer threshold value

Method and apparatus for providing debug functionality in a buffered memory channel

Memory buffer device integrating refresh logic

Method, apparatus, and system for active refresh management

Device and method for maximizing performance on a memory interface with a variable number of channels

Device and method for maximizing performance on a memory interface with a variable number of channels

Memory with reduced exposure to manufacturing related data corruption errors

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Validation of memory on-die error correction code

Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

Method, apparatus and system for responding to a row hammer event

Memory throughput increase via fine granularity of precharge management

Buffering and interleaving data transfer between a chipset and memory modules

Buffered memory module with implicit to explicit memory command expansion

Targeted aliasing single error correction (SEC) code

Method and apparatus for multiple row caches per bank

BAINS KULJIT S

Row hammer refresh command

Method and system for error management in a memory device

Memory throughput increase via fine granularity of precharge management

GREENFIELD ZVIKA

Row hammer condition monitoring

SCHAEFER ANDRE

Configuration for power reduction in DRAM