Inventor · disambiguated record
Mohamed Shaker Sarwary
Also filed as: SARWARY MOHAMED SHAKER
12 granted patents·3 pending applications·51 citations·filing 2003–2018
87Inventor score
Top patents by PatentIndex Score
15 records- 0180US7073146B2Method for clock synchronization validation in integrated circuit designATRENTA INC·Filed 2003·Granted Jul 4, 2006·30 cites·15 claims
- 0278US10387605B2System and method for managing and composing verification enginesSYNOPSYS INC·Filed 2015·Granted Aug 20, 2019·4 cites·21 claims
- 0373US7506292B2Method for clock synchronization validation in integrated circuit designATRENTA INC·Filed 2006·Granted Mar 17, 2009·6 cites·21 claims
- 0472US8607173B2Hierarchical bottom-up clock domain crossing verificationSARWARY MOHAMED SHAKER·Filed 2012·Granted Dec 10, 2013·4 cites·12 claims
- 0569US9208272B2Apparatus and method thereof for hybrid timing exception verification of an integrated circuit designSYNOPSYS INC·Filed 2013·Granted Dec 8, 2015·2 cites·12 claims
- 0669US8560988B2Apparatus and method thereof for hybrid timing exception verification of an integrated circuit designSARWARY MOHAMED SHAKER·Filed 2011·Granted Oct 15, 2013·3 cites·6 claims
- 0761US9721057B2System and method for netlist clock domain crossing verificationSYNOPSYS INC·Filed 2015·Granted Aug 1, 2017·1 cites·18 claims
- 0858US9721058B2System and method for reactive initialization based formal verification of electronic logic designSYNOPSYS INC·Filed 2015·Granted Aug 1, 2017·1 cites·16 claims
- 0948US8984457B2System and method for a hybrid clock domain crossing verificationATRENTA INC·Filed 2013·Granted Mar 17, 2015·0 cites·17 claims
- 1044US10599800B2Formal clock network analysis, visualization, verification and generationSYNOPSYS INC·Filed 2018·Granted Mar 24, 2020·0 cites·20 claims
- 1143US10289773B2Reset domain crossing management using unified power formatSYNOPSYS INC·Filed 2017·Granted May 14, 2019·0 cites·20 claims
- 1243US8656328B1System and method for abstraction of a circuit portion of an integrated circuitATRENTA INC·Filed 2013·Granted Feb 18, 2014·0 cites·28 claims
- 1343US2014282322A1System and method for filtration of error reports respective of static and quasi-static signals within an integrated circuit designATRENTA INC·Filed 2013·Application pending·0 cites
- 1440US2015234973A1System and method for abstraction of a circuit portion of an integrated circuitATRENTA INC·Filed 2014·Application pending·0 cites
- 1528US2016342727A1Method and system for checking and correcting shoot-through in rtl simulationSYNOPSYS INC·Filed 2015·Application pending·0 cites
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