Inventor · disambiguated record
Kent Harold Haselhorst
Also filed as: HASELHORST KENT H · HASELHORST KENT HAROLD
31 granted patents·4 pending applications·1,127 citations·filing 1996–2021
97Inventor score
Top patents by PatentIndex Score
35 records- 0195US6247100B1Method and system for transmitting address commands in a multiprocessor systemIBM·Filed 2000·Granted Jun 12, 2001·120 cites·8 claims
- 0294US6526469B1Bus architecture employing varying width uni-directional command busIBM·Filed 1999·Granted Feb 25, 2003·198 cites·10 claims
- 0390US6557069B1Processor-memory bus architecture for supporting multiple processorsIBM·Filed 1999·Granted Apr 29, 2003·169 cites·15 claims
- 0490US6513091B1Data routing using status-response signalsIBM·Filed 1999·Granted Jan 28, 2003·167 cites·18 claims
- 0589US5812817ACompression architecture for system memory applicationIBM·Filed 1996·Granted Sep 22, 1998·163 cites·13 claims
- 0684US7287103B2Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codesIBM·Filed 2005·Granted Oct 23, 2007·15 cites·20 claims
- 0781US8643421B1Implementing low power, single master-slave elastic bufferIBM·Filed 2013·Granted Feb 4, 2014·6 cites·17 claims
- 0877US7840744B2Rank select operation between an XIO interface and a double data rate interfaceIBM·Filed 2007·Granted Nov 23, 2010·8 cites·18 claims
- 0976US6895482B1Reordering and flushing commands in a computer memory subsystemIBM·Filed 1999·Granted May 17, 2005·79 cites·8 claims
- 1075US5710909AData compression utilization method and apparatus for computer main storeIBM·Filed 1996·Granted Jan 20, 1998·72 cites·10 claims
- 1172US6505306B1Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initializationIBM·Filed 1999·Granted Jan 7, 2003·31 cites·21 claims
- 1264US6628662B1Method and system for multilevel arbitration in a non-blocking crossbar switchIBM·Filed 1999·Granted Sep 30, 2003·52 cites·10 claims
- 1362US6532185B2Distribution of bank accesses in a multiple bank DRAM used as a data bufferIBM·Filed 2001·Granted Mar 11, 2003·8 cites·16 claims
- 1460US7752379B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2009·Granted Jul 6, 2010·1 cites·8 claims
- 1559US8219745B2Memory controller to utilize DRAM write buffersBELLOWS MARK DAVID·Filed 2004·Granted Jul 10, 2012·11 cites·20 claims
- 1657US11740901B2Centralized control of execution of quantum programIBM·Filed 2021·Granted Aug 29, 2023·0 cites·25 claims
- 1757US7272692B2Arbitration scheme for memory command selectorsIBM·Filed 2004·Granted Sep 18, 2007·6 cites·19 claims
- 1853USRE44342EBus architecture employing varying width uni-directional command busDREHMEL ROBERT ALLEN·Filed 2005·Granted Jul 2, 2013·2 cites·59 claims
- 1952US7487318B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2007·Granted Feb 3, 2009·0 cites·4 claims
- 2051US7660908B2Implementing virtual packet storage via packet work areaIBM·Filed 2003·Granted Feb 9, 2010·1 cites·9 claims
- 2150US11381634B1TFTP (trivial file transfer protocol) broadcast controllerIBM·Filed 2021·Granted Jul 5, 2022·0 cites·18 claims
- 2249US6188627B1Method and system for improving DRAM subsystem performance using burst refresh controlIBM·Filed 1999·Granted Feb 13, 2001·11 cites·17 claims
- 2348US7506081B2System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memoriesIBM·Filed 2004·Granted Mar 17, 2009·0 cites·11 claims
- 2448US7380052B2Reuse of functional data buffers for pattern buffers in XDR DRAMIBM·Filed 2004·Granted May 27, 2008·4 cites·8 claims
- 2548US7321950B2Method and apparatus for managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2005·Granted Jan 22, 2008·0 cites·14 claims
- 2647US12188964B2Spur detection in a sampled waveform in a mixed analog/digital system using the magnitude of the frequency responseIBM·Filed 2019·Granted Jan 7, 2025·0 cites·12 claims
- 2745US7617332B2Method and apparatus for implementing packet command instructions for network processingIBM·Filed 2003·Granted Nov 10, 2009·0 cites·18 claims
- 2844US2002071321A1System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memoriesIBM·Filed 2001·Application pending·0 cites
- 2942US2007136699A1Dependency matrices and methods of using the same for testing or analyzing an integrated circuitIBM·Filed 2005·Application pending·0 cites
- 3041US7925823B2Reuse of functional data buffers for pattern buffers in XDR DRAMIBM·Filed 2007·Granted Apr 12, 2011·0 cites·6 claims
- 3140US2008168206A1Methods and Apparatus for Interfacing a Processor and a MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 3239US2008229007A1Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2BELLOWS MARK D·Filed 2007·Application pending·0 cites
- 3336US8769164B2Methods and apparatus for allocating bandwidth for a network processorALFERNESS MERWIN H·Filed 2003·Granted Jul 1, 2014·0 cites·23 claims
- 3430US6523080B1Shared bus non-sequential data ordering method and apparatusIBM·Filed 1998·Granted Feb 18, 2003·2 cites·6 claims
- 3529US5748919AShared bus non-sequential data ordering method and apparatusIBM·Filed 1996·Granted May 5, 1998·1 cites·3 claims
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