Inventor · disambiguated record
Anirban Rahut
Also filed as: RAHUT ANIRBAN
24 granted patents·1 pending application·231 citations·filing 2002–2025
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
25 records- 0198US9256501B1High availability scheduler for scheduling map-reduce searchesSPLUNK INC·Filed 2015·Granted Feb 9, 2016·33 cites·30 claims
- 0297US9047246B1High availability schedulerSPLUNK INC·Filed 2014·Granted Jun 2, 2015·40 cites·30 claims
- 0393US7430728B1Method and apparatus for selecting programmable interconnects to reduce clock skewXILINX INC·Filed 2005·Granted Sep 30, 2008·28 cites·15 claims
- 0485US7389485B1Methods of routing low-power designs in programmable logic devices having heterogeneous routing architecturesXILINX INC·Filed 2006·Granted Jun 17, 2008·16 cites·18 claims
- 0581US2025265273A1Search result replication management in a search head clusterSPLUNK INC·Filed 2025·Application pending·0 cites
- 0680US9983954B2High availability scheduler for scheduling searches of time stamped eventsSPLUNK INC·Filed 2015·Granted May 29, 2018·2 cites·30 claims
- 0780US7424697B1Assigning inputs of look-up tables to improve a design implementation in a programmable logic deviceXILINX INC·Filed 2007·Granted Sep 9, 2008·13 cites·20 claims
- 0879US6766504B1Interconnect routing using logic levelsXILINX INC·Filed 2002·Granted Jul 20, 2004·26 cites·22 claims
- 0978US12282497B1Search result replication management in a search head clusterSPLUNK INC·Filed 2023·Granted Apr 22, 2025·0 cites·17 claims
- 1078US8010923B1Latch based optimization during implementation of circuit designs for programmable logic devicesXILINX INC·Filed 2008·Granted Aug 30, 2011·7 cites·16 claims
- 1178US6952813B1Method and apparatus for selecting programmable interconnects to reduce clock skewXILINX INC·Filed 2003·Granted Oct 4, 2005·20 cites·23 claims
- 1275US7904860B1Method and apparatus for selecting programmable interconnects to reduce clock skewXILINX INC·Filed 2008·Granted Mar 8, 2011·5 cites·20 claims
- 1371US7735039B1Methods of estimating net delays in tile-based PLD architecturesXILINX INC·Filed 2007·Granted Jun 8, 2010·6 cites·20 claims
- 1467US7725868B1Method and apparatus for facilitating signal routing within a programmable logic deviceXILINX INC·Filed 2007·Granted May 25, 2010·3 cites·2 claims
- 1566US8015535B1Run-time efficient methods for routing large multi-fanout netsXILINX INC·Filed 2008·Granted Sep 6, 2011·2 cites·20 claims
- 1666US7797665B1Patterns for routing nets in a programmable logic deviceXILINX INC·Filed 2007·Granted Sep 14, 2010·3 cites·20 claims
- 1766US7620923B1Run-time efficient methods for routing large multi-fanout netsXILINX INC·Filed 2008·Granted Nov 17, 2009·2 cites·4 claims
- 1866US7051312B1Upper-bound calculation for placed circuit design performanceXILINX INC·Filed 2003·Granted May 23, 2006·11 cites·34 claims
- 1963US11704341B2Search result replication management in a search head clusterSPLUNK INC·Filed 2018·Granted Jul 18, 2023·0 cites·30 claims
- 2062US10698777B2High availability scheduler for scheduling map-reduce searches based on a leader stateSPLUNK INC·Filed 2018·Granted Jun 30, 2020·0 cites·30 claims
- 2162US7306977B1Method and apparatus for facilitating signal routing within a programmable logic deviceXILINX INC·Filed 2003·Granted Dec 11, 2007·7 cites·12 claims
- 2260US7376926B1Run-time efficient methods for routing large multi-fanout netsXILINX INC·Filed 2005·Granted May 20, 2008·1 cites·7 claims
- 2358US10133806B2Search result replication in a search head clusterSPLUNK INC·Filed 2014·Granted Nov 20, 2018·0 cites·31 claims
- 2458US7076758B1Using router feedback for placement improvements for logic designXILINX INC·Filed 2003·Granted Jul 11, 2006·6 cites·22 claims
- 2548US8146041B1Latch based optimization during implementation of circuit designs for programmable logic devicesSRINIVASAN SANKARANARAYANAN·Filed 2011·Granted Mar 27, 2012·0 cites·10 claims
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