Inventor · disambiguated record
Carole Lambert
Also filed as: LAMBERT CAROLE
54 granted patents·6 pending applications·1,104 citations·filing 2009–2022
99Inventor score
Top patents by PatentIndex Score
60 records- 0199US8847329B2Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contactsBECKER SCOTT T·Filed 2013·Granted Sep 30, 2014·63 cites·27 claims
- 0299US8836045B2Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode trackTELA INNOVATIONS INC·Filed 2013·Granted Sep 16, 2014·57 cites·25 claims
- 0399US8735995B2Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode trackBECKER SCOTT T·Filed 2013·Granted May 27, 2014·57 cites·26 claims
- 0499US8701071B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2013·Granted Apr 15, 2014·64 cites·20 claims
- 0599US8575706B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrodeBECKER SCOTT T·Filed 2010·Granted Nov 5, 2013·76 cites·26 claims
- 0699US8405163B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level featureBECKER SCOTT T·Filed 2010·Granted Mar 26, 2013·86 cites·24 claims
- 0799US8395224B2Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodesBECKER SCOTT T·Filed 2010·Granted Mar 12, 2013·92 cites·25 claims
- 0898US9202779B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2014·Granted Dec 1, 2015·42 cites·21 claims
- 0998US8863063B2Finfet transistor circuitBECKER SCOTT T·Filed 2013·Granted Oct 14, 2014·125 cites·26 claims
- 1098US8853794B2Integrated circuit within semiconductor chip including cross-coupled transistor configurationTELA INNOVATIONS INC·Filed 2014·Granted Oct 7, 2014·16 cites·30 claims
- 1197US9009641B2Circuits with linear finfet structuresBECKER SCOTT T·Filed 2013·Granted Apr 14, 2015·34 cites·52 claims
- 1297US8866197B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level featureBECKER SCOTT T·Filed 2010·Granted Oct 21, 2014·19 cites·24 claims
- 1397US8729606B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channelsBECKER SCOTT T·Filed 2010·Granted May 20, 2014·15 cites·30 claims
- 1497US8569841B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channelBECKER SCOTT T·Filed 2010·Granted Oct 29, 2013·16 cites·31 claims
- 1597US8453094B2Enforcement of semiconductor structure regularity for localized transistors and interconnectKORNACHUK STEPHEN·Filed 2009·Granted May 28, 2013·95 cites·22 claims
- 1697US8448102B2Optimizing layout of irregular structures in regular layout contextKORNACHUK STEPHEN·Filed 2009·Granted May 21, 2013·105 cites·26 claims
- 1796US9213792B2Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methodsTELA INNOVATIONS INC·Filed 2015·Granted Dec 15, 2015·7 cites·30 claims
- 1894US8847331B2Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structuresTELA INNOVATIONS INC·Filed 2014·Granted Sep 30, 2014·6 cites·30 claims
- 1994US8816402B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistorBECKER SCOTT T·Filed 2010·Granted Aug 26, 2014·8 cites·27 claims
- 2094US8735944B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistorsBECKER SCOTT T·Filed 2010·Granted May 27, 2014·8 cites·30 claims
- 2193US9536899B2Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Jan 3, 2017·4 cites·30 claims
- 2293US9117050B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specificationsBECKER SCOTT T·Filed 2012·Granted Aug 25, 2015·6 cites·25 claims
- 2393US8872283B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level featureTELA INNOVATIONS INC·Filed 2013·Granted Oct 28, 2014·6 cites·24 claims
- 2493US8552509B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistorsBECKER SCOTT T·Filed 2010·Granted Oct 8, 2013·7 cites·26 claims
- 2593US8552508B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layerBECKER SCOTT T·Filed 2010·Granted Oct 8, 2013·7 cites·24 claims
- 2692US9871056B2Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2016·Granted Jan 16, 2018·3 cites·30 claims
- 2791US9245081B2Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methodsTELA INNOVATIONS INC·Filed 2014·Granted Jan 26, 2016·4 cites·30 claims
- 2891US9208279B2Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methodsTELA INNOVATIONS INC·Filed 2014·Granted Dec 8, 2015·4 cites·30 claims
- 2991US9081931B2Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layerBECKER SCOTT T·Filed 2013·Granted Jul 14, 2015·4 cites·24 claims
- 3090US8592872B2Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level featureBECKER SCOTT T·Filed 2012·Granted Nov 26, 2013·4 cites·26 claims
- 3189US8669594B2Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channelsBECKER SCOTT T·Filed 2010·Granted Mar 11, 2014·4 cites·26 claims
- 3289US8558322B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level featureBECKER SCOTT T·Filed 2010·Granted Oct 15, 2013·4 cites·24 claims
- 3389US8405162B2Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level regionBECKER SCOTT T·Filed 2010·Granted Mar 26, 2013·4 cites·19 claims
- 3488US8853793B2Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line endsTELA INNOVATIONS INC·Filed 2013·Granted Oct 7, 2014·3 cites·25 claims
- 3588US8729643B2Cross-coupled transistor circuit including offset inner gate contactsBECKER SCOTT T·Filed 2013·Granted May 20, 2014·3 cites·44 claims
- 3687US9754878B2Semiconductor chip including a chip level based on a layout that includes both regular and irregular wiresTELA INNOVATIONS INC·Filed 2013·Granted Sep 5, 2017·7 cites·22 claims
- 3787US8835989B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specificationsBECKER SCOTT T·Filed 2010·Granted Sep 16, 2014·3 cites·27 claims
- 3887US8785979B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layerBECKER SCOTT T·Filed 2010·Granted Jul 22, 2014·3 cites·26 claims
- 3987US8785978B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layerBECKER SCOTT T·Filed 2010·Granted Jul 22, 2014·3 cites·26 claims
- 4087US8772839B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layerBECKER SCOTT T·Filed 2010·Granted Jul 8, 2014·3 cites·26 claims
- 4187US8742463B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contactsBECKER SCOTT T·Filed 2010·Granted Jun 3, 2014·3 cites·27 claims
- 4287US8742462B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specificationsBECKER SCOTT T·Filed 2010·Granted Jun 3, 2014·3 cites·25 claims
- 4387US8669595B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specificationsBECKER SCOTT T·Filed 2010·Granted Mar 11, 2014·3 cites·25 claims
- 4487US8587034B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layerBECKER SCOTT T·Filed 2010·Granted Nov 19, 2013·3 cites·27 claims
- 4587US8581303B2Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layerBECKER SCOTT T·Filed 2010·Granted Nov 12, 2013·3 cites·27 claims
- 4687US8581304B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationshipsBECKER SCOTT T·Filed 2010·Granted Nov 12, 2013·3 cites·26 claims
- 4787US8564071B2Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contactBECKER SCOTT T·Filed 2010·Granted Oct 22, 2013·3 cites·24 claims
- 4884US10658385B2Cross-coupled transistor circuit defined on four gate electrode tracksTELA INNOVATIONS INC·Filed 2013·Granted May 19, 2020·2 cites·50 claims
- 4984US9530734B2Enforcement of semiconductor structure regularity for localized transistors and interconnectTELA INNOVATIONS INC·Filed 2015·Granted Dec 27, 2016·3 cites·19 claims
- 5079US8680583B2Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channelsBECKER SCOTT T·Filed 2010·Granted Mar 25, 2014·1 cites·26 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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