Inventor · disambiguated record
Khaled Hasnat
Also filed as: HASNAT KHALED
23 granted patents·6 pending applications·165 citations·filing 2003–2024
95Inventor score
Top patents by PatentIndex Score
29 records- 0198US10651153B2Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bondingINTEL CORP·Filed 2018·Granted May 12, 2020·67 cites·17 claims
- 0296US9378839B2Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2014·Granted Jun 28, 2016·15 cites·18 claims
- 0396US8797806B2Apparatus and methods including source gatesGODA AKIRA·Filed 2011·Granted Aug 5, 2014·22 cites·25 claims
- 0494US11195575B1Memory array with shorting structure on a dummy array thereof, and method of providing sameINTEL CORP·Filed 2020·Granted Dec 7, 2021·5 cites·19 claims
- 0594US9219070B23-D memory arraysMICRON TECHNOLOGY INC·Filed 2013·Granted Dec 22, 2015·21 cites·26 claims
- 0693US9779816B2Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2016·Granted Oct 3, 2017·9 cites·20 claims
- 0791US11211126B2Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2020·Granted Dec 28, 2021·2 cites·20 claims
- 0889US10170189B2Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2017·Granted Jan 1, 2019·5 cites·21 claims
- 0987US10923450B2Memory arrays with bonded and shared logic circuitryINTEL CORP·Filed 2019·Granted Feb 16, 2021·4 cites·17 claims
- 1085US2025124982A1Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1184US10783967B2Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2018·Granted Sep 22, 2020·3 cites·20 claims
- 1283US7547597B2Direct alignment scheme between multiple lithography layersINTEL CORP·Filed 2006·Granted Jun 16, 2009·8 cites·19 claims
- 1375US12148474B2Apparatus and methods including source gatesMICRON TECHNOLOGY INC·Filed 2021·Granted Nov 19, 2024·0 cites·20 claims
- 1464US10409506B2Sense flags in a memory deviceMICRON TECHNOLOGY INC·Filed 2018·Granted Sep 10, 2019·0 cites·20 claims
- 1562US9135998B2Sense operation flags in a memory deviceAHMED SHAFQAT·Filed 2010·Granted Sep 15, 2015·1 cites·20 claims
- 1660US10126967B2Sense operation flags in a memory deviceMICRON TECHNOLOGY INC·Filed 2016·Granted Nov 13, 2018·0 cites·15 claims
- 1759US11500446B2Reducing power consumption in nonvolatile memory due to standby leakage currentINTEL CORP·Filed 2019·Granted Nov 15, 2022·1 cites·21 claims
- 1856US11029861B2Sense flags in a memory deviceMICRON TECHNOLOGY INC·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 1952US10854746B2Channel conductivity in memory structuresINTEL CORP·Filed 2018·Granted Dec 1, 2020·0 cites·21 claims
- 2050US10804280B2Memory device with vertical string driversINTEL CORP·Filed 2018·Granted Oct 13, 2020·0 cites·15 claims
- 2150US2022359441A1Three-dimensional (3d) nand component with control circuitry across multiple wafersINTEL CORP·Filed 2021·Application pending·0 cites
- 2249US9519582B2Sense operation flags in a memory deviceMICRON TECHNOLOGY INC·Filed 2015·Granted Dec 13, 2016·0 cites·21 claims
- 2348US10861867B2Memory device with reduced capacitanceINTEL CORP·Filed 2018·Granted Dec 8, 2020·0 cites·14 claims
- 2448US2022190029A1Tier architecture for 3-dimensional cross point memoryINTEL CORP·Filed 2020·Application pending·0 cites
- 2545US7087943B2Direct alignment scheme between multiple lithography layersINTEL CORP·Filed 2003·Granted Aug 8, 2006·2 cites·12 claims
- 2641US2019043868A1Three-dimensional (3d) memory with control circuitry and array in separately processed and bonded wafersINTEL CORP·Filed 2018·Application pending·0 cites
- 2738US10515973B2Wordline bridge in a 3D memory arrayINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·21 claims
- 2834US2020152650A1Memory device with a split staircaseINTEL CORP·Filed 2018·Application pending·0 cites
- 2932US2014370664A1Word line and bit line processing for cross-point memoriesPANGAL KIRAN·Filed 2013·Application pending·0 cites
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