Inventor · disambiguated record
Hyeokjin Lim
Also filed as: LIM HYEOKJIN · LIM HYEOKJIN BRUCE
18 granted patents·7 pending applications·53 citations·filing 2015–2023
91Inventor score
Files withQUALCOMM INC25
Top patents by PatentIndex Score
25 records- 0197US9831272B2Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenchesQUALCOMM INC·Filed 2016·Granted Nov 28, 2017·26 cites·30 claims
- 0295US11710733B2Vertical power grid standard cell architectureQUALCOMM INC·Filed 2020·Granted Jul 25, 2023·4 cites·12 claims
- 0395US11404374B2Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methodsQUALCOMM INC·Filed 2020·Granted Aug 2, 2022·3 cites·17 claims
- 0486US10605859B2Visible alignment markers/landmarks for CAD-to-silicon backside image alignmentQUALCOMM INC·Filed 2016·Granted Mar 31, 2020·5 cites·17 claims
- 0581US10600866B2Standard cell architecture for gate tie-offQUALCOMM INC·Filed 2018·Granted Mar 24, 2020·2 cites·12 claims
- 0680US10777640B2Standard cell architecture for gate tie-offQUALCOMM INC·Filed 2020·Granted Sep 15, 2020·1 cites·23 claims
- 0779US10175571B2Hybrid coloring methodology for multi-pattern technologyQUALCOMM INC·Filed 2016·Granted Jan 8, 2019·3 cites·25 claims
- 0874US9577639B1Source separated cellQUALCOMM INC·Filed 2015·Granted Feb 21, 2017·3 cites·30 claims
- 0972US9960231B2Standard cell architecture for parasitic resistance reductionQUALCOMM INC·Filed 2016·Granted May 1, 2018·2 cites·20 claims
- 1070US10490543B2Placement methodology to remove fillerQUALCOMM INC·Filed 2017·Granted Nov 26, 2019·1 cites·13 claims
- 1170US9935100B2Power rail inbound middle of line (MOL) routingQUALCOMM INC·Filed 2015·Granted Apr 3, 2018·2 cites·15 claims
- 1268US10236886B2Multiple via structure for high performance standard cellsQUALCOMM INC·Filed 2016·Granted Mar 19, 2019·1 cites·12 claims
- 1367US10784345B2Standard cell architecture for gate tie-offQUALCOMM INC·Filed 2020·Granted Sep 22, 2020·0 cites·19 claims
- 1465US11133803B2Multiple via structure for high performance standard cellsQUALCOMM INC·Filed 2020·Granted Sep 28, 2021·0 cites·20 claims
- 1558US10965289B2Metal oxide semiconductor device of an integrated circuitQUALCOMM INC·Filed 2019·Granted Mar 30, 2021·0 cites·8 claims
- 1651US2024170488A1Integrated circuit cell including column stacked pinsQUALCOMM INC·Filed 2022·Application pending·0 cites
- 1750US2024266342A1Column divided multi-height architectureQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1850US2024249056A1Engineering change order (eco) spare cellQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1949US11437379B2Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuitsQUALCOMM INC·Filed 2020·Granted Sep 6, 2022·0 cites·21 claims
- 2049US11290109B1Multibit multi-height cell to improve pin accessibilityQUALCOMM INC·Filed 2020·Granted Mar 29, 2022·0 cites·18 claims
- 2146US2022115405A1Heterogeneous height logic cell architectureQUALCOMM INC·Filed 2020·Application pending·0 cites
- 2241US2020020795A1Self-aligned gate cut for optimal power and routingQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2340US10692808B2High performance cell design in a technology with high density metal routingQUALCOMM INC·Filed 2017·Granted Jun 23, 2020·0 cites·13 claims
- 2438US2019252408A1Staggered self aligned gate contactQUALCOMM INC·Filed 2018·Application pending·0 cites
- 2536US2021058076A1Hybrid fin flip flop circuit architectureQUALCOMM INC·Filed 2019·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →