Inventor · disambiguated record
James Nadir
Also filed as: NADIR JAMES
12 granted patents·508 citations·filing 1978–2018
93Inventor score
Top patents by PatentIndex Score
12 records- 0196US4257095ASystem bus arbitration, circuitry and methodologyINTEL CORP·Filed 1978·Granted Mar 17, 1981·169 cites·21 claims
- 0289US5517136AOpportunistic time-borrowing domino logicINTEL CORP·Filed 1995·Granted May 14, 1996·73 cites·34 claims
- 0376US5210845AController for two-way set associative cacheINTEL CORP·Filed 1990·Granted May 11, 1993·75 cites·3 claims
- 0466US5339399ACache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input busINTEL CORP·Filed 1991·Granted Aug 16, 1994·55 cites·4 claims
- 0558US5479641AMethod and apparatus for overlapped timing of cache operations including reading and writing with parity checkingINTEL CORP·Filed 1993·Granted Dec 26, 1995·35 cites·14 claims
- 0653US5737569AMultiport high speed memory having contention arbitration capability without standby delayINTEL CORP·Filed 1996·Granted Apr 7, 1998·29 cites·2 claims
- 0749US5450565ACircuit and method for selecting a set in a set associative cacheINTEL CORP·Filed 1993·Granted Sep 12, 1995·22 cites·11 claims
- 0846US5530833AApparatus and method for updating LRU pointer in a controller for two-way set associative cacheINTEL CORP·Filed 1995·Granted Jun 25, 1996·18 cites·3 claims
- 0946US5367659ATag initialization in a controller for two-way set associative cacheINTEL CORP·Filed 1994·Granted Nov 22, 1994·18 cites·3 claims
- 1035US5724547ALRU pointer updating in a controller for two-way set associative cacheINTEL CORP·Filed 1996·Granted Mar 3, 1998·7 cites·20 claims
- 1134US5392417AProcessor cycle tracking in a controller for two-way set associative cacheINTEL CORP·Filed 1994·Granted Feb 21, 1995·7 cites·2 claims
- 1233US10921018B2Self-sealing vent assemblySRIBHASHYAM SASHRIK·Filed 2018·Granted Feb 16, 2021·0 cites·12 claims
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