Inventor · disambiguated record
Lance Hacking
Also filed as: HACKING LANCE · HACKING LANCE E
29 granted patents·6 pending applications·371 citations·filing 1997–2024
96Inventor score
Top patents by PatentIndex Score
35 records- 0189US9189439B2Interface logic for a multi-core system-on-a-chip (SoC)INTEL CORP·Filed 2013·Granted Nov 17, 2015·8 cites·19 claims
- 0288US6014735AInstruction set extension using prefixesINTEL CORP·Filed 1998·Granted Jan 11, 2000·150 cites·20 claims
- 0385US11714998B2Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bitsINTEL CORP·Filed 2020·Granted Aug 1, 2023·3 cites·25 claims
- 0477US6073210ASynchronization of weakly ordered write combining operations using a fencing mechanismINTEL CORP·Filed 1998·Granted Jun 6, 2000·76 cites·20 claims
- 0575US12288153B2Schedule-aware tensor distribution moduleINTEL CORP·Filed 2024·Granted Apr 29, 2025·0 cites·20 claims
- 0674US7315952B2Power state coordination between devices sharing power-managed resourcesINTEL CORP·Filed 2004·Granted Jan 1, 2008·19 cites·29 claims
- 0770US8289850B2Interconnect bandwidth throttlerHACKING LANCE·Filed 2011·Granted Oct 16, 2012·2 cites·8 claims
- 0868US9372768B2Debug interfaceINTEL CORP·Filed 2013·Granted Jun 21, 2016·3 cites·25 claims
- 0968US7272741B2Hardware coordination of power management activitiesINTEL CORP·Filed 2004·Granted Sep 18, 2007·13 cites·31 claims
- 1067US8050177B2Interconnect bandwidth throttlerINTEL CORP·Filed 2008·Granted Nov 1, 2011·3 cites·10 claims
- 1166US7360103B2P-state feedback to operating system with hardware coordinationINTEL CORP·Filed 2004·Granted Apr 15, 2008·14 cites·48 claims
- 1265US2024005135A1Accelerating neural networks with low precision-based multiplication and exploiting sparsity in higher order bitsINTEL CORP·Filed 2023·Application pending·0 cites
- 1363US8412855B2Write combining protocol between processors and chipsetsCRETA KENNETH C·Filed 2010·Granted Apr 2, 2013·2 cites·17 claims
- 1463US7877619B2Power mode control method and circuitryRACHAKONDA RAMANA·Filed 2007·Granted Jan 25, 2011·3 cites·20 claims
- 1560US7676603B2Write combining protocol between processors and chipsetsINTEL CORP·Filed 2004·Granted Mar 9, 2010·6 cites·28 claims
- 1657US8392728B2Reducing idle leakage power in an ICHACKING LANCE·Filed 2006·Granted Mar 5, 2013·2 cites·4 claims
- 1757US6978357B1Method and apparatus for performing cache segment flush and cache segment invalidation operationsINTEL CORP·Filed 1998·Granted Dec 20, 2005·32 cites·38 claims
- 1856US11907827B2Schedule-aware tensor distribution moduleINTEL CORP·Filed 2019·Granted Feb 20, 2024·0 cites·18 claims
- 1956US8656411B2Technique for monitoring activity within an integrated circuitHACKING LANCE E·Filed 2008·Granted Feb 18, 2014·1 cites·10 claims
- 2056US6862679B2Synchronization of load operations using load fence instruction in pre-serialization/post-serialization modeINTEL CORP·Filed 2001·Granted Mar 1, 2005·5 cites·21 claims
- 2153US9189302B2Technique for monitoring activity within an integrated circuitINTEL CORP·Filed 2014·Granted Nov 17, 2015·0 cites·13 claims
- 2253US8650629B2Interface logic for a multi-core system-on-a-chip (SoC)RACHAKONDA RAMANA·Filed 2009·Granted Feb 11, 2014·1 cites·20 claims
- 2350US8312309B2Technique for promoting determinism among multiple clock domainsHENDRICKSON ERIC L·Filed 2008·Granted Nov 13, 2012·1 cites·20 claims
- 2449US9830954B2Method and system for dynamic power management of memoriesHACKING LANCE E·Filed 2011·Granted Nov 28, 2017·1 cites·14 claims
- 2547US11347828B2Methods, apparatus, articles of manufacture to perform accelerated matrix multiplicationINTEL CORP·Filed 2020·Granted May 31, 2022·0 cites·24 claims
- 2647US7284118B2Method and apparatus for synchronizing load operationsINTEL CORP·Filed 2004·Granted Oct 16, 2007·1 cites·18 claims
- 2745US6289431B1Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entriesINTEL CORP·Filed 1998·Granted Sep 11, 2001·17 cites·22 claims
- 2844US7249245B2Globally observing load operations prior to fence instruction and post-serialization modesINTEL CORP·Filed 2004·Granted Jul 24, 2007·0 cites·17 claims
- 2944US2006080461A1Packet exchange for controlling system power modesWILCOX JEFFREY R·Filed 2004·Application pending·0 cites
- 3043US7707350B2Bus interconnect switching mechanismINTEL CORP·Filed 2008·Granted Apr 27, 2010·0 cites·9 claims
- 3141US2003018960A1System and a method of sorting perfomance data from one or more system configurationsFiled 2001·Application pending·0 cites
- 3241US2023004430A1Estimation of power profiles for neural network models running on ai acceleratorsINTEL CORP·Filed 2022·Application pending·0 cites
- 3340US2014108684A1Interconnect bandwidth throttlerHACKING LANCE·Filed 2012·Application pending·0 cites
- 3436US5946713AMemory attribute paletteINTEL CORP·Filed 1997·Granted Aug 31, 1999·8 cites·18 claims
- 3535US2018189587A1Technologies for feature detection and trackingINTEL CORP·Filed 2017·Application pending·0 cites
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