Inventor

SHEARER ROBERT A

US137 patents

⚠️ This page may combine multiple inventors who share the name “SHEARER ROBERT A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEARER ROBERT A

IBM

Dynamic thread status retrieval using inter-thread communication

Dynamic virtual software pipelining on a network on chip

Multiple spacial indexes for dynamic scene management in graphics rendering

Pixel color accumulation in a ray tracing image processing system

Monitoring software pipeline performance on a network on chip

Instruction set architecture with opcode lookup using memory attribute

Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively

Methods and systems for texture prefetching based on a most recently hit primitive algorithm

Dynamic load-based credit distribution

Self-healing link sequence counts within a circular buffer

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Indirect instruction predication

Indirect instruction predication

Extensible execution unit interface architecture with multiple decode logic and multiple execution units

Local instruction loop buffer utilizing execution unit register file

Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core

Dynamic thread status retrieval using inter-thread communication

Dynamic thread status retrieval using inter-thread communication

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Instruction set architecture with secure clear instructions for protecting processing unit architected state information

Allocating cache for use as a dedicated local storage

Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores

Near neighbor data cache sharing

Graphics rendering on a network on chip

Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

MEJDRICH ERIC O

Performance event triggering through direct interthread communication on a network on chip

Software pipelining on a network on chip

Single step mode in a software pipeline within a highly threaded network on a chip microprocessor

Instruction buffer bypass of target instruction in response to partial flush

Software pipelining on a network on chip

DMA-based acceleration of command push buffer between host and target devices

Parallelized ray tracing

Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threads

Propagating shared state changes to multiple threads within a multithreaded processing environment

Sequential processing in network on chip nodes by threads generating message containing payload and pointer for nanokernel to access algorithm to be executed on payload in another node

Rolling texture context data structure for maintaining texture data in a multithreaded image processing pipeline

MUFF ADAM J

Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels

Memory address translation-based data encryption with integrated encryption engine

Memory address translation-based data encryption/compression

SHEARER ROBERT A

Updating frame divisions based on ray tracing image processing system performance

Integrated acceleration data structure for physics and ray tracing workload

HOOVER RUSSELL D

Network on chip with a low latency, high bandwidth application messaging interconnect

Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data

FOWLER DAVID K

Accelerated data structure optimization based upon view orientation

Physical rendering with textured bounding volume primitive mapping

KUESEL JAMIE R

Indirect inter-thread communication using a shared pool of inboxes

BROWN JEFFREY D

Multi-core processor with internal voting-based built in self test (BIST)

HEIL TIMOTHY H

Memory management among levels of cache in a memory hierarchy

GREENWOOD JASON

Inter-thread communication with software security