Inventor · disambiguated record
Nidhir Kumar
Also filed as: KUMAR NIDHIR
16 granted patents·2 pending applications·73 citations·filing 2009–2024
91Inventor score
Top patents by PatentIndex Score
18 records- 0190US9007855B2Data signal receiver and method of calibrating a data signal receiverADVANCED RISC MACH LTD·Filed 2012·Granted Apr 14, 2015·19 cites·20 claims
- 0285US8780655B1Method and apparatus for aligning a clock signal and a data strobe signal in a memory systemADVANCED RISC MACH LTD·Filed 2012·Granted Jul 15, 2014·12 cites·19 claims
- 0378US9213359B2Interface for controlling the phase alignment of clock signals for a recipient deviceADVANCED RISC MACH LTD·Filed 2012·Granted Dec 15, 2015·5 cites·20 claims
- 0477US9105327B2Memory controller using a data strobe signal and method of calibrating data strobe signal in a memory controllerADVANCED RISC MACH LTD·Filed 2013·Granted Aug 11, 2015·5 cites·20 claims
- 0576US9042188B2Memory controller and method of calibrating a memory controllerADVANCED RISC MACH LTD·Filed 2013·Granted May 26, 2015·4 cites·19 claims
- 0675US8421516B2Apparatus and method providing an interface between a first voltage domain and a second voltage domainKUMAR NIDHIR·Filed 2010·Granted Apr 16, 2013·6 cites·24 claims
- 0772US10297310B2System and method for multi-cycle write levelingINVECAS TECH PVT LTD·Filed 2016·Granted May 21, 2019·4 cites·6 claims
- 0871US8427198B1Reduced quantization error I/O resistor calibratorCHERUKU SRIDHAR·Filed 2011·Granted Apr 23, 2013·5 cites·22 claims
- 0971US7924056B2Low voltage differential signalling driverADVANCED RISC MACH LTD·Filed 2009·Granted Apr 12, 2011·8 cites·15 claims
- 1068US8773185B2Calibration of delay chainsADVANCED RISC MACH LTD·Filed 2012·Granted Jul 8, 2014·3 cites·20 claims
- 1155US2024363153A1Signal retiming within memory systemsMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1249US8502568B2Receiver circuit with high input voltage protectionDWIVEDI SANDEEP·Filed 2010·Granted Aug 6, 2013·1 cites·17 claims
- 1348US10725681B2Method for calibrating the read latency of a DDR DRAM moduleSYNOPSYS INC·Filed 2016·Granted Jul 28, 2020·1 cites·7 claims
- 1447US7986504B2Distributing power to an integrated circuitADVANCED RISC MACH LTD·Filed 2009·Granted Jul 26, 2011·0 cites·17 claims
- 1533US10775836B2Method for cycle accurate data transfer in a skewed synchronous clock domainSYNOPSYS INC·Filed 2016·Granted Sep 15, 2020·0 cites·5 claims
- 1631US10312886B2Asynchronous clock gating circuitINVECAS TECH PVT LTD·Filed 2016·Granted Jun 4, 2019·0 cites·9 claims
- 1728US10504569B2System and method for controlling phase alignment of clock signalsINVECAS TECH PVT LTD·Filed 2016·Granted Dec 10, 2019·0 cites·7 claims
- 1828US2014002156A1Duty cycle correction within an integrated circuitDWIVEDI SANDEEP·Filed 2012·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →