Inventor · disambiguated record
Philipp Panitz
Also filed as: PANITZ PHILIPP
14 granted patents·1 pending application·47 citations·filing 2007–2015
88Inventor score
Top patents by PatentIndex Score
15 records- 0192US9207995B2Mechanism to speed-up multithreaded execution by register file write port reallocationBOERSMA MAARTEN J·Filed 2011·Granted Dec 8, 2015·26 cites·12 claims
- 0274US8903882B2Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program productBOERSMA MAARTEN J·Filed 2011·Granted Dec 2, 2014·4 cites·13 claims
- 0371US9164725B2Apparatus and method for calculating an SHA-2 hash function in a general purpose processorBOERSMA MAARTEN J·Filed 2011·Granted Oct 20, 2015·3 cites·20 claims
- 0470US8407654B2Glitch power reductionBUECHNER THOMAS·Filed 2012·Granted Mar 26, 2013·3 cites·20 claims
- 0569US8015527B2Routing of wires of an electronic circuitIBM·Filed 2008·Granted Sep 6, 2011·5 cites·16 claims
- 0666US8972961B2Instruction scheduling approach to improve processor performanceKOEHL JUERGEN·Filed 2011·Granted Mar 3, 2015·2 cites·11 claims
- 0766US8935685B2Instruction scheduling approach to improve processor performanceKOEHL JUERGEN·Filed 2012·Granted Jan 13, 2015·2 cites·3 claims
- 0859US8627263B2Gate configuration determination and selection from standard cell libraryBUECHNER THOMAS·Filed 2012·Granted Jan 7, 2014·1 cites·16 claims
- 0959US8612911B2Estimating power consumption of an electronic circuitBUECHNER THOMAS·Filed 2012·Granted Dec 17, 2013·1 cites·20 claims
- 1055US8959276B2Byte selection and steering logic for combined byte shift and byte permute vector unitIBM·Filed 2014·Granted Feb 17, 2015·0 cites·7 claims
- 1151US8959275B2Byte selection and steering logic for combined byte shift and byte permute vector unitIBM·Filed 2012·Granted Feb 17, 2015·0 cites·7 claims
- 1250US9256430B2Instruction scheduling approach to improve processor performanceIBM·Filed 2015·Granted Feb 9, 2016·0 cites·14 claims
- 1344US2008059933A1Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated CircuitIBM·Filed 2007·Application pending·0 cites
- 1441US8731858B2Method and system for calculating timing delay in a repeater network in an electronic circuitBUEHLER MARKUS·Filed 2009·Granted May 20, 2014·0 cites·20 claims
- 1531US9043673B2Techniques for reusing components of a logical operations functional block as an error correction code correction unitIBM·Filed 2013·Granted May 26, 2015·0 cites·20 claims
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