Inventor

GALBI DUANE E

US21 patents

⚠️ This page may combine multiple inventors who share the name “GALBI DUANE E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GALBI DUANE E

IBM

Low voltage programmable storage element

ZAG fuse for reduced blow-current application

Low voltage programmable storage element

Fast check bit write for a semiconductor memory

Clocking circuit with increasing delay as supply voltage VDD

Off-chip driver with voltage regulated predrive

Memory device having asymmetrical CAS to data input/output mapping and applications thereof

Boosted drive system for master/local word line memory architecture

Stable voltage reference circuit with high Vt devices

INTEL CORP

ECC coding for high speed implementation

Translation cache and configurable ECC memory for reducing ECC memory overhead

Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs

Memory striping approach that interleaves sub protected data words

Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth

Regulating application of clock to control current rush (DI/DT)

Remote storage for hardware microservices hosted on XPUs and SOC-XPU platforms

MINDSPEED TECH INC

Enhancing performance by pre-fetching and caching data directly in a communication processor&#39;s register set

Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task

COMPAQ COMPUTER CORP

Method and apparatus for performing two pass quality video compression through pipelining and buffer management

HEWLETT PACKARD DEVELOPMENT CO

Method and apparatus for performing two pass quality video compression through pipelining and buffer management

GALBI DUANE E

Apparatuses for register file with novel bit cell implementation

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set