Inventor · disambiguated record
Glenn J. Hinton
Also filed as: HINTON GLENN · HINTON GLENN J
155 granted patents·11 pending applications·6,822 citations·filing 1986–2022
99Inventor score
Top patents by PatentIndex Score
166 records- 0197US9690493B2Two-level system main memoryINTEL CORP·Filed 2015·Granted Jun 27, 2017·23 cites·61 claims
- 0296US8612676B2Two-level system main memoryDAHLEN ERIC J·Filed 2010·Granted Dec 17, 2013·100 cites·20 claims
- 0396US5721855AMethod for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder bufferINTEL CORP·Filed 1996·Granted Feb 24, 1998·335 cites·23 claims
- 0496US5623628AComputer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queueINTEL CORP·Filed 1994·Granted Apr 22, 1997·296 cites·13 claims
- 0595US9786338B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2016·Granted Oct 10, 2017·9 cites·20 claims
- 0695US9378142B2Apparatus and method for implementing a multi-level memory hierarchy having different operating modesRAMANUJAN RAJ K·Filed 2011·Granted Jun 28, 2016·27 cites·32 claims
- 0795US9087584B2Two-level system main memoryINTEL CORP·Filed 2013·Granted Jul 21, 2015·23 cites·28 claims
- 0895US6425073B2Method and apparatus for staggering execution of an instructionINTEL CORP·Filed 2001·Granted Jul 23, 2002·85 cites·59 claims
- 0995US5604877AMethod and apparatus for resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1994·Granted Feb 18, 1997·209 cites·28 claims
- 1094US9600416B2Apparatus and method for implementing a multi-level memory hierarchyRAMANUJAN RAJ K·Filed 2011·Granted Mar 21, 2017·23 cites·31 claims
- 1192US10163468B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Dec 25, 2018·5 cites·20 claims
- 1291US9418700B2Bad block management mechanismRAMANUJAN RAJ K·Filed 2012·Granted Aug 16, 2016·15 cites·19 claims
- 1391US5574871AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1994·Granted Nov 12, 1996·122 cites·17 claims
- 1490US9424034B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2013·Granted Aug 23, 2016·8 cites·29 claims
- 1589US11200176B2Dynamic partial power down of memory-side cache in a 2-level memory hierarchyINTEL CORP·Filed 2020·Granted Dec 14, 2021·2 cites·12 claims
- 1689US5751996AMethod and apparatus for processing memory-type information within a microprocessorINTEL CORP·Filed 1996·Granted May 12, 1998·147 cites·52 claims
- 1789US5555432ACircuit and method for scheduling instructions by predicting future availability of resources required for executionINTEL CORP·Filed 1994·Granted Sep 10, 1996·108 cites·7 claims
- 1889US5526510AMethod and apparatus for implementing a single clock cycle line replacement in a data cache unitINTEL CORP·Filed 1994·Granted Jun 11, 1996·157 cites·12 claims
- 1988US8386823B2Method and apparatus for cost and power efficient, scalable operating system independent servicesINTEL CORP·Filed 2012·Granted Feb 26, 2013·7 cites·20 claims
- 2088US5881262AMethod and apparatus for blocking execution of and storing load operations during their executionINTEL CORP·Filed 1997·Granted Mar 9, 1999·126 cites·45 claims
- 2188US5778245AMethod and apparatus for dynamic allocation of multiple buffers in a processorINTEL CORP·Filed 1994·Granted Jul 7, 1998·131 cites·22 claims
- 2288US5751983AOut-of-order processor with a memory subsystem which handles speculatively dispatched load operationsFiled 1995·Granted May 12, 1998·140 cites·26 claims
- 2387US10170165B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Jan 1, 2019·4 cites·20 claims
- 2487US10141033B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Nov 27, 2018·4 cites·20 claims
- 2587US10102126B2Apparatus and method for implementing a multi-level memory hierarchy having different operating modesINTEL CORP·Filed 2016·Granted Oct 16, 2018·4 cites·20 claims
- 2687US10102888B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Oct 16, 2018·4 cites·32 claims
- 2787US7856633B1LRU cache replacement for a partitioned set associative cacheINTEL CORP·Filed 2000·Granted Dec 21, 2010·49 cites·35 claims
- 2887US7523323B2Method and apparatus for quick resumptionINTEL CORP·Filed 2005·Granted Apr 21, 2009·14 cites·19 claims
- 2987US7366881B2Method and apparatus for staggering execution of an instructionINTEL CORP·Filed 2005·Granted Apr 29, 2008·11 cites·19 claims
- 3086US10153011B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Dec 11, 2018·4 cites·20 claims
- 3186US6925553B2Staggering execution of a single packed data instruction using the same circuitINTEL CORP·Filed 2003·Granted Aug 2, 2005·30 cites·26 claims
- 3286US6047369AFlag renaming and flag masks within register alias tableINTEL CORP·Filed 1994·Granted Apr 4, 2000·122 cites·48 claims
- 3385US6735688B1Processor having replay architecture with fast and slow replay pathsINTEL CORP·Filed 2000·Granted May 11, 2004·41 cites·23 claims
- 3485US5627985ASpeculative and committed resource files in an out-of-order processorINTEL CORP·Filed 1994·Granted May 6, 1997·112 cites·33 claims
- 3585US4811208AStack frame cache on a microprocessor chipINTEL CORP·Filed 1986·Granted Mar 7, 1989·101 cites·3 claims
- 3684US7757045B2Synchronizing recency information in an inclusive cache hierarchyINTEL CORP·Filed 2006·Granted Jul 13, 2010·14 cites·23 claims
- 3784US6721866B2Unaligned memory operandsINTEL CORP·Filed 2001·Granted Apr 13, 2004·37 cites·24 claims
- 3884US6018786ATrace based instruction cachingINTEL CORP·Filed 1997·Granted Jan 25, 2000·107 cites·46 claims
- 3984US5812839ADual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unitINTEL CORP·Filed 1997·Granted Sep 22, 1998·118 cites·32 claims
- 4083US10365832B2Two-level system main memoryINTEL CORP·Filed 2017·Granted Jul 30, 2019·2 cites·18 claims
- 4183US10153012B2Multiple register memory access instructions, processors, methods, and systemsINTEL CORP·Filed 2017·Granted Dec 11, 2018·3 cites·18 claims
- 4283US5586278AMethod and apparatus for state recovery following branch misprediction in an out-of-order microprocessorINTEL CORP·Filed 1996·Granted Dec 17, 1996·109 cites·18 claims
- 4382US10719443B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2019·Granted Jul 21, 2020·2 cites·19 claims
- 4482US8171219B2Method and system to perform caching based on file-level heuristicsTRIKA SANJEEV N·Filed 2009·Granted May 1, 2012·12 cites·36 claims
- 4582US5613083ATranslation lookaside buffer that is non-blocking in response to a miss for use within a microprocessor capable of processing speculative instructionsINTEL CORP·Filed 1994·Granted Mar 18, 1997·93 cites·30 claims
- 4681US6079014AProcessor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural stateINTEL CORP·Filed 1997·Granted Jun 20, 2000·101 cites·23 claims
- 4781US5671444AMethods and apparatus for caching data in a non-blocking manner using a plurality of fill buffersINTEL CORPORAITON·Filed 1996·Granted Sep 23, 1997·104 cites·39 claims
- 4881US5584038AEntry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversedINTEL CORP·Filed 1996·Granted Dec 10, 1996·89 cites·8 claims
- 4981US5420991AApparatus and method for maintaining processing consistency in a computer system having multiple processorsINTEL CORP·Filed 1994·Granted May 30, 1995·89 cites·20 claims
- 5080US10241912B2Apparatus and method for implementing a multi-level memory hierarchyINTEL CORP·Filed 2017·Granted Mar 26, 2019·2 cites·32 claims
Showing the top 50 of 166 patent records by PatentIndex Score.
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