Inventor
CHAUDHARY KAMAL
US36 patents
⚠️ This page may combine multiple inventors who share the name “CHAUDHARY KAMAL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
30 patentsUS7075333B1Jul 11, 2006
Programmable circuit optionally configurable as a lookup table or a wide multiplexer
XILINX INC159 citations99
US6448808B2Sep 10, 2002
Interconnect structure for a programmable logic device
XILINX INC225 citations99
US6086631AJul 11, 2000
Post-placement residual overlap removal method for core-based PLD programming process
XILINX INC242 citations99
US5920202AJul 6, 1999
Configurable logic element with ability to evaluate five and six input functions
XILINX INC121 citations99
US5914616AJun 22, 1999
FPGA repeatable interconnect structure with hierarchical interconnect lines
XILINX INC495 citations99
US5889411AMar 30, 1999
FPGA having logic element carry chains capable of generating wide XOR functions
XILINX INC279 citations99
US5963050AOct 5, 1999
Configurable logic element with fast feedback paths
XILINX INC129 citations98
US5942913AAug 24, 1999
FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines
XILINX INC91 citations98
US5936424AAug 10, 1999
High speed bus with tree structure for selecting bus driver
XILINX INC128 citations98
US6336208B1Jan 1, 2002
Delay optimized mapping for programmable gate arrays with multiple sized lookup tables
XILINX INC60 citations96
US6292022B2Sep 18, 2001
Interconnect structure for a programmable logic device
XILINX INC31 citations96
US6204690B1Mar 20, 2001
FPGA architecture with offset interconnect lines
XILINX INC45 citations96
US6107827AAug 22, 2000
FPGA CLE with two independent carry chains
XILINX INC59 citations96
US6051992AApr 18, 2000
Configurable logic element with ability to evaluate five and six input functions
XILINX INC44 citations96
US5677638AOct 14, 1997
High speed tristate bus with multiplexers for selecting bus driver
XILINX INC28 citations93
US7111214B1Sep 19, 2006
Circuits and methods for testing programmable logic devices using lookup tables and carry chains
XILINX INC20 citations92
US6415425B1Jul 2, 2002
Method for analytical placement of cells using density surface representations
XILINX INC38 citations92
US6362648B1Mar 26, 2002
Multiplexer for implementing logic functions in a programmable logic device
XILINX INC19 citations92
US6201410B1Mar 13, 2001
Wide logic gate implemented in an FPGA configurable logic element
XILINX INC20 citations92
US6124731ASep 26, 2000
Configurable logic element with ability to evaluate wide logic functions
XILINX INC37 citations92
US6081914AJun 27, 2000
Method for implementing priority encoders using FPGA carry logic
XILINX INC32 citations92
US8010923B1Aug 30, 2011
Latch based optimization during implementation of circuit designs for programmable logic devices
XILINX INC7 citations84
US7536661B1May 19, 2009
Incremental placement during physical synthesis
XILINX INC12 citations84
US7428718B1Sep 23, 2008
Enhanced incremental placement during physical synthesis
XILINX INC9 citations84
US7072815B1Jul 4, 2006
Relocation of components for post-placement optimization
XILINX INC14 citations83
US7146590B1Dec 5, 2006
Congestion estimation for programmable logic devices
XILINX INC10 citations74
US6484298B1Nov 19, 2002
Method and apparatus for automatic timing-driven implementation of a circuit design
XILINX INC11 citations73
US7058915B1Jun 6, 2006
Pin reordering during placement of circuit designs
XILINX INC3 citations63
US7853914B1Dec 14, 2010
Fanout-optimization during physical synthesis for placed circuit designs
XILINX INC3 citations60
US7590960B1Sep 15, 2009
Placing partitioned circuit designs within iterative implementation flows
XILINX INC3 citations58