Inventor

KAVALIEROS JACK T

US426 patents

⚠️ This page may combine multiple inventors who share the name “KAVALIEROS JACK T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAVALIEROS JACK T

INTEL CORP

Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers

Tri-gate patterning using dual layer gate stack

Multigate device with recessed strain regions

Dielectric interface for group III-V semiconductor device

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Forming ultra-shallow junctions

Method of ion implanting for tri-gate devices

Integrating n-type and p-type metal gate transistors

Fabrication of germanium nanowire transistors

Transistor having tensile strained channel and system including same

Method for fabricating transistor with thinned channel

Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Integrating n-type and p-type metal gate transistors

integrating n-type and P-type metal gate transistors

Integrating n-type and p-type metal gate transistors

Dual crystal orientation circuit devices on the same substrate

Transistors with high concentration of boron doped germanium

Dielectric interface for group III-V semiconductor device

Forming a non-planar transistor having a quantum well channel

CMOS devices with a single work function gate electrode and method of fabrication

Strain-inducing semiconductor regions

Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method

Tensile strained NMOS transistor using group III-N source/drain regions

Apparatus and method for selectively recessing spacers on multi-gate devices

Forming a type I heterostructure in a group IV semiconductor

Sb-based CMOS devices

Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors

Pinning layer for low resistivity N-type source drain ohmic contacts

Non-planar gate all-around device and method of fabrication thereof

PILLARISETTY RAVI

Trench confined epitaxially grown device layer(s)

Non-planar germanium quantum well devices

Trench confined epitaxially grown device layer(s)

Non-planar germanium quantum well devices

RACHMADY WILLY

Non-planar gate all-around device and method of fabrication thereof

Variable gate width for gate all-around transistors

Multi-gate device having a T-shaped gate structure

CEA STEPHEN M

High mobility strained channels for fin-based transistors

Non-planar device having uniaxially strained semiconductor body and method of making same

Methods and apparatus to reduce layout based strain variations in non-planar transistor structures

KAVALIEROS JACK T

Two-dimensional condensation for uniaxially strained semiconductor fins

Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

DATTA SUMAN

Strain inducing semiconductor regions

Strain-inducing semiconductor regions

MURTHY ANAND S

Transistors with high concentration of boron doped germanium

JIN BEEN-YIH

Fabrication of germanium nanowire transistors

DOYLE BRIAN S

CMOS devices with a single work function gate electrode and method of fabrication

CAPPELLANI ANNALISA

Semiconductor device with isolated body portion

RADOSAVLJEVIC MARKO

Conductivity improvements for III-V semiconductor devices

MAJHI PRASHANT

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains