Inventor · disambiguated record
Suryanarayana Duggirala
Also filed as: DUGGIRALA SURYANARAYANA
13 granted patents·1 pending application·208 citations·filing 1999–2023
93Inventor score
Files withSYNOPSYS INC14
Top patents by PatentIndex Score
14 records- 0196US7900105B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2010·Granted Mar 1, 2011·15 cites·35 claims
- 0290US7418640B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2004·Granted Aug 26, 2008·28 cites·7 claims
- 0389US11829692B1Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QOR)SYNOPSYS INC·Filed 2021·Granted Nov 28, 2023·4 cites·16 claims
- 0489US6766501B1System and method for high-level test planning for layoutSYNOPSYS INC·Filed 2002·Granted Jul 20, 2004·34 cites·26 claims
- 0586US7774663B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Aug 10, 2010·8 cites·7 claims
- 0685US7596733B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Sep 29, 2009·8 cites·7 claims
- 0784US7836367B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·7 cites·56 claims
- 0880US6434733B1System and method for high-level test planning for layoutSYNOPSYS INC·Filed 1999·Granted Aug 13, 2002·39 cites·26 claims
- 0979US6405355B1Method for placement-based scan-in and scan-out ports selectionSYNOPSYS INC·Filed 1999·Granted Jun 11, 2002·43 cites·22 claims
- 1076US12333227B1Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)SYNOPSYS INC·Filed 2023·Granted Jun 17, 2025·0 cites·20 claims
- 1171US7836368B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2009·Granted Nov 16, 2010·3 cites·28 claims
- 1265US7743299B2Dynamically reconfigurable shared scan-in test architectureSYNOPSYS INC·Filed 2008·Granted Jun 22, 2010·2 cites·5 claims
- 1351US2023205960A1Design for testability circuitry placement within an integrated circuit designSYNOPSYS INC·Filed 2022·Application pending·0 cites
- 1449US6269463B1Method and system for automatically determining transparency behavior of non-scan cells for combinational automatic test pattern generationSYNOPSYS INC·Filed 1999·Granted Jul 31, 2001·17 cites·21 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →