Inventor · disambiguated record
Sudipta Kundu
Also filed as: KUNDU SUDIPTA
8 granted patents·2 pending applications·17 citations·filing 2008–2022
80Inventor score
Top patents by PatentIndex Score
10 records- 0182US10515170B1Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checkingSYNOPSYS INC·Filed 2018·Granted Dec 24, 2019·4 cites·20 claims
- 0278US9369397B1Apparatus to achieve quality of service (QoS) without requiring fabric speedupJUNIPER NETWORKS INC·Filed 2014·Granted Jun 14, 2016·4 cites·20 claims
- 0372US11507719B1Accelerating formal property verification across design versions using sequential equivalence checkingSYNOPSYS INC·Filed 2021·Granted Nov 22, 2022·1 cites·20 claims
- 0472US8914758B1Equivalence checking using structural analysis on data flow graphsSYNOPSYS INC·Filed 2013·Granted Dec 16, 2014·3 cites·34 claims
- 0566US8448145B2Methods and systems for reducing verification conditions for concurrent programs using mutually atomic transactionsGANAI MALAY K·Filed 2009·Granted May 21, 2013·4 cites·17 claims
- 0665US9973437B2Apparatus to achieve quality of service (QOS) without requiring fabric speedupJUNIPER NETWORKS INC·Filed 2016·Granted May 15, 2018·1 cites·20 claims
- 0750US12481814B1Performing automatic sign-off for clock gating verification using toggle cover propertiesSYNOPSYS INC·Filed 2022·Granted Nov 25, 2025·0 cites·20 claims
- 0847US11556676B2Scalable formal security verification of circuit designsSYNOPSYS INC·Filed 2020·Granted Jan 17, 2023·0 cites·20 claims
- 0946US2009132991A1Partial order reduction for scalable testing in system level designNEC LAB AMERICA INC·Filed 2008·Application pending·0 cites
- 1038US2021216694A1Debugging non-detected faults using sequential equivalence checkingSYNOPSYS INC·Filed 2020·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →