Inventor

WARNES LIDIA

US37 patents

⚠️ This page may combine multiple inventors who share the name “WARNES LIDIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WARNES LIDIA

INTEL CORP

Dynamically composable computing system, a data center, and method for dynamically composing a computing system

Tenant based allocation for pooled memory

Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

Ballooning for multi-tiered pooled memory

Ballooning for multi-tiered pooled memory

Memory access tracing

Memory pool management

Apparatus and method for intelligent memory page management

Creating robustness scores for selected portions of a computing infrastructure

Memory thin provisioning using memory pools

Method to minimize hot/cold page detection overhead on running workloads

HEWLETT PACKARD ENTPR DEV LP

Validation of a repair to a selected row of data

Error counters on a memory device

Post package repair (PPR) data in non-volatile memory

Partial backup during runtime for memory modules with volatile memory and non-volatile memory

Post package repair (PPR) data in non-volatile memory

Memory controller

Memory erasure information in cache lines

Status for generated data image

Handling errors during run time backups

HEWLETT PACKARD DEVELOPMENT CO

Parallel memory device rank selection

Communicating between a native fully buffered dual in-line memory module protocol and a double data rate synchronous dynamic random access memory protocol

On-line memory testing

Employing a native fully buffered dual in-line memory module protocol to write parallel protocol memory module channels

Memory module including voltage sense monitoring interface

Differential on-line termination

Determining whether a right to use memory modules in a reliability mode has been acquired

Modular DIMM carrier and riser slot

WARNES LIDIA

Increasing the number of ranks per channel

Rank sparing system and method

Memory module that includes a memory module copy engine for copying data from an active memory die to a spare memory die

Parallel memory device rank selection

SHAW MARK

Redundant memory to mask DRAM failures

HEWLETT PACKARD DEVELOPMENT CO LP

Platform error correction

ESPINOZA-IBARRA RICARDO ERNESTO

Power controller

LEE TEDDY

Memory module including environmental optimization

GOLDSTEIN MARTIN

Serial connection external interface from printed circuit board translation to parallel memory protocol