Inventor · disambiguated record
Doug Carmean
Also filed as: CARMEAN DOUG
12 granted patents·1 pending application·70 citations·filing 2002–2020
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
13 records- 0194US8615647B2Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power stateHUM HERBERT·Filed 2008·Granted Dec 24, 2013·34 cites·20 claims
- 0292US8930722B2Distribution of tasks among asymmetric processing elementsSPRANGLE ERIC·Filed 2009·Granted Jan 6, 2015·16 cites·21 claims
- 0382US11054890B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Jul 6, 2021·3 cites·18 claims
- 0482US9760162B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Sep 12, 2017·3 cites·8 claims
- 0578US9870046B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Jan 16, 2018·2 cites·12 claims
- 0674US11366511B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2020·Granted Jun 21, 2022·0 cites·29 claims
- 0773US9910483B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Mar 6, 2018·1 cites·4 claims
- 0872US9939882B2Systems and methods for migrating processes among asymmetrical processing coresINTEL CORP·Filed 2013·Granted Apr 10, 2018·1 cites·6 claims
- 0963US10437320B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2016·Granted Oct 8, 2019·0 cites·15 claims
- 1063US10409360B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2016·Granted Sep 10, 2019·0 cites·9 claims
- 1163US10386915B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2016·Granted Aug 20, 2019·0 cites·12 claims
- 1263US7080209B2Method and apparatus for processing a load-lock instruction using a relaxed lock protocolINTEL CORP·Filed 2002·Granted Jul 18, 2006·10 cites·24 claims
- 1340US2004123078A1Method and apparatus for processing a load-lock instruction using a scoreboard mechanismHUM HERBERT H·Filed 2002·Application pending·0 cites
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