Inventor · disambiguated record
Paul G. Davis
Also filed as: DAVIS PAUL G · DAVIS PAUL GREGORY
55 granted patents·4 pending applications·2,558 citations·filing 1996–2014
99Inventor score
Top patents by PatentIndex Score
59 records- 0198US7581121B2System for a memory device having a power down mode and methodRAMBUS INC·Filed 2005·Granted Aug 25, 2009·76 cites·21 claims
- 0298US6401167B1High performance cost optimized memoryRAMBUS INC·Filed 1998·Granted Jun 4, 2002·168 cites·67 claims
- 0398US6343352B1Method and apparatus for two step memory write operationsRAMBUS INC·Filed 1998·Granted Jan 29, 2002·154 cites·43 claims
- 0498US6343042B1DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2000·Granted Jan 29, 2002·99 cites·9 claims
- 0598US6310814B1Rambus DRAM (RDRAM) apparatus and method for performing refresh operationsRAMBUS INC·Filed 2000·Granted Oct 30, 2001·195 cites·40 claims
- 0698US6154821AMethod and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domainRAMBUS INC·Filed 1998·Granted Nov 28, 2000·237 cites·24 claims
- 0797US7287119B2Integrated circuit memory device with delayed write command processingRAMBUS INC·Filed 2007·Granted Oct 23, 2007·40 cites·23 claims
- 0897US7197611B2Integrated circuit memory device having write latency functionRAMBUS INC·Filed 2005·Granted Mar 27, 2007·54 cites·27 claims
- 0997US7047375B2Memory system and method for two step memory write operationsRAMBUS INC·Filed 2005·Granted May 16, 2006·40 cites·24 claims
- 1097US6266292B1DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2000·Granted Jul 24, 2001·82 cites·46 claims
- 1197US6075744ADram core refresh with reduced spike currentRAMBUS INC·Filed 1998·Granted Jun 13, 2000·110 cites·11 claims
- 1296US6842864B1Method and apparatus for configuring access times of memory devicesRAMBUS INC·Filed 2000·Granted Jan 11, 2005·99 cites·32 claims
- 1396US6597616B2DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2002·Granted Jul 22, 2003·73 cites·32 claims
- 1496US6075730AHigh performance cost optimized memory with delayed memory writesRAMBUS INC·Filed 1998·Granted Jun 13, 2000·182 cites·6 claims
- 1595US6868474B2High performance cost optimized memoryRAMBUS INC·Filed 2002·Granted Mar 15, 2005·58 cites·6 claims
- 1694US6378018B1Memory device and system including a low power interfaceINTEL CORP·Filed 1998·Granted Apr 23, 2002·224 cites·32 claims
- 1793US8756395B2Controlling DRAM at time DRAM ready to receive command when exiting power downBARTH RICHARD M·Filed 2012·Granted Jun 17, 2014·12 cites·22 claims
- 1893US6889300B2Memory system and method for two step write operationsRAMBUS INC·Filed 2001·Granted May 3, 2005·50 cites·17 claims
- 1991US6473439B1Method and apparatus for fail-safe resynchronization with minimum latencyRAMBUS INC·Filed 1998·Granted Oct 29, 2002·140 cites·22 claims
- 2090US8140805B2Memory component having write operation with multiple time periodsDAVIS PAUL G·Filed 2010·Granted Mar 20, 2012·9 cites·23 claims
- 2190US7571330B2System and module including a memory device having a power down modeRAMBUS INC·Filed 2005·Granted Aug 4, 2009·14 cites·30 claims
- 2290US6949958B2Phase comparator capable of tolerating a non-50% duty-cycle clocksRAMBUS INC·Filed 2002·Granted Sep 27, 2005·52 cites·5 claims
- 2389USD654124SPortable travel exercise apparatusDAVIS PAUL G·Filed 2009·Granted Feb 14, 2012·40 cites·1 claims
- 2489US7330953B2Memory system having delayed write timingRAMBUS INC·Filed 2007·Granted Feb 12, 2008·11 cites·28 claims
- 2588US7330952B2Integrated circuit memory device having delayed write timing based on read response timeRAMBUS INC·Filed 2007·Granted Feb 12, 2008·10 cites·28 claims
- 2687US8589717B1Serial peripheral interfaceDAVIS PAUL G·Filed 2010·Granted Nov 19, 2013·18 cites·20 claims
- 2787US6553452B2Synchronous memory device having a temperature registerRAMBUS INC·Filed 2002·Granted Apr 22, 2003·31 cites·45 claims
- 2886US7288973B2Method and apparatus for fail-safe resynchronization with minimum latencyRAMBUS INC·Filed 2005·Granted Oct 30, 2007·11 cites·22 claims
- 2982US7496709B2Integrated circuit memory device having delayed write timing based on read response timeRAMBUS INC·Filed 2007·Granted Feb 24, 2009·6 cites·50 claims
- 3082US6778458B2Dram core refresh with reduced spike currentRAMBUS INC·Filed 2003·Granted Aug 17, 2004·18 cites·22 claims
- 3181US7360050B2Integrated circuit memory device having delayed write capabilityRAMBUS INC·Filed 2007·Granted Apr 15, 2008·6 cites·31 claims
- 3280US7574616B2Memory device having a power down exit registerRAMBUS INC·Filed 2004·Granted Aug 11, 2009·14 cites·41 claims
- 3379US8920294B2Suspension training deviceDAVIS PAUL G·Filed 2010·Granted Dec 30, 2014·9 cites·17 claims
- 3478US8296540B2Method and apparatus for adjusting the performance of a synchronous memory systemGARLEPP BRUNO WERNER·Filed 2008·Granted Oct 23, 2012·8 cites·34 claims
- 3576US7142475B2Memory device having a configurable oscillator for refresh operationRAMBUS INC·Filed 2004·Granted Nov 28, 2006·13 cites·20 claims
- 3674US6009487AMethod and apparatus for setting a current of an output driver for the high speed busRAMBUS INC·Filed 1996·Granted Dec 28, 1999·70 cites·55 claims
- 3772US8127152B2Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit modeBARTH RICHARD M·Filed 2004·Granted Feb 28, 2012·10 cites·25 claims
- 3872US7861030B2Method and apparatus for updating data in ROM using a CAMMICROCHIP TECH INC·Filed 2008·Granted Dec 28, 2010·8 cites·18 claims
- 3968US7337294B2Method and apparatus for adjusting the performance of a synchronous memory systemRAMBUS INC·Filed 2006·Granted Feb 26, 2008·2 cites·20 claims
- 4067US7421548B2Memory system and method for two step memory write operationsRAMBUS INC·Filed 2005·Granted Sep 2, 2008·3 cites·19 claims
- 4166US7349279B2Memory Device Having a Configurable Oscillator for Refresh OperationRAMBUS INC·Filed 2006·Granted Mar 25, 2008·3 cites·22 claims
- 4266US6757789B2Apparatus and method for maximizing information transfers over limited interconnect resourcesRAMBUS INC·Filed 2002·Granted Jun 29, 2004·9 cites·26 claims
- 4366US6513103B1Method and apparatus for adjusting the performance of a synchronous memory systemRAMBUS INC·Filed 1997·Granted Jan 28, 2003·31 cites·81 claims
- 4463US9375596B2Suspension training devicePOWER STRAPS INC·Filed 2014·Granted Jun 28, 2016·3 cites·20 claims
- 4563US8019958B2Memory write signaling and methods thereofRAMBUS INC·Filed 2010·Granted Sep 13, 2011·1 cites·24 claims
- 4662US7870357B2Memory system and method for two step memory write operationsRAMBUS INC·Filed 2008·Granted Jan 11, 2011·2 cites·22 claims
- 4762US7437527B2Memory device with delayed issuance of internal write commandRAMBUS INC·Filed 2007·Granted Oct 14, 2008·2 cites·29 claims
- 4858US7793039B2Interface for a semiconductor memory device and method for controlling the interfaceRAMBUS INC·Filed 2009·Granted Sep 7, 2010·1 cites·34 claims
- 4958US6178130B1Apparatus and method for refreshing subsets of memory devices in a memory systemRAMBUS INC·Filed 1998·Granted Jan 23, 2001·15 cites·21 claims
- 5056US6347354B1Apparatus and method for maximizing information transfers over limited interconnect resourcesRAMBUS INC·Filed 1998·Granted Feb 12, 2002·25 cites·37 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
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