Inventor · disambiguated record
Ryan Rakvic
Also filed as: RAKVIC RYAN · RAKVIC RYAN N
13 granted patents·3 pending applications·108 citations·filing 2001–2012
91Inventor score
Top patents by PatentIndex Score
16 records- 0191US8108863B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2005·Granted Jan 31, 2012·30 cites·24 claims
- 0287US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 0385US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 0481US8205200B2Compiler-based scheduling optimization hints for user-level threadsLIAO SHIH-WEI·Filed 2005·Granted Jun 19, 2012·13 cites·24 claims
- 0574US7665000B2Meeting point thread characterizationINTEL CORP·Filed 2007·Granted Feb 16, 2010·7 cites·15 claims
- 0670US7228402B2Predicate register file write by an instruction with a pending instruction having data dependencyINTEL CORP·Filed 2002·Granted Jun 5, 2007·15 cites·20 claims
- 0768US8887174B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersHANKINS RICHARD A·Filed 2011·Granted Nov 11, 2014·2 cites·10 claims
- 0864US8839258B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2012·Granted Sep 16, 2014·1 cites·29 claims
- 0957US6668306B2Non-vital loadsINTEL CORP·Filed 2001·Granted Dec 23, 2003·5 cites·37 claims
- 1053US6954848B2Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediatelyINTEL CORP·Filed 2002·Granted Oct 11, 2005·3 cites·24 claims
- 1150US7120749B2Cache mechanismINTEL CORP·Filed 2004·Granted Oct 10, 2006·1 cites·23 claims
- 1248US7216201B2Parallel cacheletsINTEL CORP·Filed 2006·Granted May 8, 2007·0 cites·24 claims
- 1342US7424576B2Parallel cacheletsINTEL CORP·Filed 2001·Granted Sep 9, 2008·0 cites·17 claims
- 1441US2003065906A1ASAP instruction cachingFiled 2001·Application pending·0 cites
- 1541US2003131345A1Employing value prediction with the compilerFiled 2002·Application pending·0 cites
- 1640US2007074217A1Scheduling optimizations for user-level threadsRAKVIC RYAN·Filed 2005·Application pending·0 cites
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