Inventor · disambiguated record
Muralikumar A. Padaparambil
Also filed as: PADAPARAMBIL MURALIKUMAR A
10 granted patents·1 pending application·123 citations·filing 2004–2008
88Inventor score
Top patents by PatentIndex Score
11 records- 0192US7161846B2Dual-edge triggered multiplexer flip-flop and methodSEIKO EPSON CORP·Filed 2004·Granted Jan 9, 2007·61 cites·17 claims
- 0286US7864084B2Serializer architecture for serial communicationsSEIKO EPSON CORP·Filed 2008·Granted Jan 4, 2011·19 cites·8 claims
- 0363US7079055B2Low-power serializer with half-rate clocking and methodSEIKO EPSON CORP·Filed 2004·Granted Jul 18, 2006·13 cites·13 claims
- 0460US7804911B2Dual demodulation mode AM radioSEIKO EPSON CORP·Filed 2007·Granted Sep 28, 2010·2 cites·34 claims
- 0560US7187222B2CMOS master/slave flip-flop with integrated multiplexorSEIKO EPSON CORP·Filed 2004·Granted Mar 6, 2007·9 cites·7 claims
- 0659US7038497B2Differential current mode phase/frequency detector circuitSEIKO EPSON CORP·Filed 2004·Granted May 2, 2006·7 cites·52 claims
- 0757US7034594B2Differential master/slave CML latchSEIKO EPSON CORP·Filed 2004·Granted Apr 25, 2006·9 cites·18 claims
- 0855US7392334B2Circuits and methods for high speed and low power data serializationSEIKO EPSON CORP·Filed 2006·Granted Jun 24, 2008·3 cites·20 claims
- 0945US8000671B2Dual threshold demodulation in an amplitude modulation radio receiverSEIKO EPSON CORP·Filed 2008·Granted Aug 16, 2011·0 cites·20 claims
- 1033US2007013424A1Differential dual-edge triggered multiplexer flip-flop and methodPADAPARAMBIL MURALIKUMAR A·Filed 2005·Application pending·0 cites
- 1131US7042251B2Multi-function differential logic gateSEIKO EPSON CORP·Filed 2004·Granted May 9, 2006·0 cites·15 claims
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