Inventor

FEGHALI WAJDI K

US146 patents

⚠️ This page may combine multiple inventors who share the name “FEGHALI WAJDI K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FEGHALI WAJDI K

INTEL CORP

Architecture and instruction set for implementing advanced encryption standard (AES)

Systems and methods for performing matrix compress and decompress instructions

Technologies for flexibly compressing and decompressing data

High-performance hashing system

Techniques for data compression verification

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Architecture and instruction set for implementing advanced encryption standard (AES)

System and method for cryptography processing units and multiplier

Systems and methods for performing matrix compress and decompress instructions

Systems and methods for performing matrix compress and decompress instructions

Architecture and instruction set for implementing advanced encryption standard (AES)

Architecture and instruction set for implementing advanced encryption standard (AES)

SM3 hash function message expansion processors, methods, systems, and instructions

Architecture and instruction set for implementing advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Instruction and logic to provide a secure cipher hash round functionality

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Rotate instructions that complete execution either without writing or reading flags

Techniques for parallel data compression

Instructions and logic to provide SIMD SM3 cryptographic hashing functionality

Method and apparatus for performing a shift and exclusive or operation in a single instruction

SMS4 acceleration processors, methods, systems, and instructions

Apparatus and method for performing RC4 ciphering

Apparatus and method for implementing the KASUMI ciphering process

Add instructions to add three source operands

Systems and methods for performing matrix compress and decompress instructions

Architecture and instruction set for implementing advanced encryption standard (AES)

Method and apparatus to process SHA-2 secure hashing algorithm

Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality

Rotate instructions that complete execution either without writing or reading flags

Method and apparatus to process SHA-2 secure hashing algorithm

GOPAL VINODH

Matrix multiply accumulate instruction

SIMD integer multiply-accumulate instruction for multi-precision arithmetic

Filter for network intrusion and virus detection

Method and apparatus for performing a shift and exclusive or operation in a single instruction

Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage

Method for signing and verifying data using multiple hash algorithms and digests in PKCS

Unified system architecture for elliptic-curve cryptography

Add instructions to add three source operands

Method and apparatus for advanced encryption standard (AES) block cipher

Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography

Rotate instructions that complete execution without reading carry flag

GUERON SHAY

Architecture and instruction set for implementing advanced encryption standard (AES)

Flexible architecture and instruction for advanced encryption standard (AES)

YAP KIRK S

Method and apparatus to process KECCAK secure hashing algorithm

Method and apparatus to process SHA-2 secure hashing algorithm

RADHAKRISHNAN SIVAKUMAR

Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic

FEGHALI WAJDI K

Cryptographic system, method and multiplier