Inventor · disambiguated record
Matthew R. Tubbs
Also filed as: TUBBS MATTHEW · TUBBS MATTHEW R · TUBBS MATTHEW RAY
124 granted patents·10 pending applications·1,050 citations·filing 2003–2016
99Inventor score
Top patents by PatentIndex Score
134 records- 0199US8310497B2Anisotropic texture filtering with texture data prefetchingCOMPARAN MIGUEL·Filed 2012·Granted Nov 13, 2012·133 cites·24 claims
- 0299US8217953B2Anisotropic texture filtering with texture data prefetchingCOMPARAN MIGUEL·Filed 2008·Granted Jul 10, 2012·135 cites·2 claims
- 0396US7809925B2Processing unit incorporating vectorizable execution unitIBM·Filed 2007·Granted Oct 5, 2010·52 cites·21 claims
- 0495US8661455B2Performance event triggering through direct interthread communication on a network on chipMEJDRICH ERIC O·Filed 2009·Granted Feb 25, 2014·45 cites·14 claims
- 0595US8356162B2Execution unit with data dependent conditional write instructionsIBM·Filed 2008·Granted Jan 15, 2013·45 cites·20 claims
- 0693US8140832B2Single step mode in a software pipeline within a highly threaded network on a chip microprocessorMEJDRICH ERIC O·Filed 2009·Granted Mar 20, 2012·34 cites·16 claims
- 0793US7873816B2Pre-loading context states by inactive hardware thread in advance of context switchIBM·Filed 2008·Granted Jan 18, 2011·36 cites·21 claims
- 0893US7814303B2Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectivelyIBM·Filed 2008·Granted Oct 12, 2010·34 cites·25 claims
- 0992US9582277B2Indirect instruction predicationIBM·Filed 2016·Granted Feb 28, 2017·6 cites·5 claims
- 1092US9292290B2Instruction set architecture with opcode lookup using memory attributeIBM·Filed 2013·Granted Mar 22, 2016·13 cites·11 claims
- 1192US9147078B2Instruction set architecture with secure clear instructions for protecting processing unit architected state informationIBM·Filed 2013·Granted Sep 29, 2015·15 cites·12 claims
- 1291US8751830B2Memory address translation-based data encryption/compressionMUFF ADAM J·Filed 2012·Granted Jun 10, 2014·16 cites·22 claims
- 1391US8350846B2Updating ray traced acceleration data structures between frames based on changing perspectiveIBM·Filed 2009·Granted Jan 8, 2013·25 cites·25 claims
- 1490US8593459B2Tree insertion depth adjustment based on view frustum and distance cullingMEJDRICH ERIC OLIVER·Filed 2012·Granted Nov 26, 2013·11 cites·25 claims
- 1589US8619078B2Parallelized ray tracingMEJDRICH ERIC O·Filed 2010·Granted Dec 31, 2013·12 cites·20 claims
- 1689US8587596B2Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threadsMEJDRICH ERIC O·Filed 2010·Granted Nov 19, 2013·12 cites·23 claims
- 1788US9710274B2Extensible execution unit interface architecture with multiple decode logic and multiple execution unitsIBM·Filed 2016·Granted Jul 18, 2017·4 cites·16 claims
- 1888US9619234B2Indirect instruction predicationIBM·Filed 2016·Granted Apr 11, 2017·4 cites·20 claims
- 1987US10042417B2Branch prediction with power usage prediction and controlIBM·Filed 2016·Granted Aug 7, 2018·4 cites·19 claims
- 2087US9354887B2Instruction buffer bypass of target instruction in response to partial flushMEJDRICH ERIC O·Filed 2010·Granted May 31, 2016·11 cites·24 claims
- 2187US9183399B2Instruction set architecture with secure clear instructions for protecting processing unit architected state informationIBM·Filed 2013·Granted Nov 10, 2015·8 cites·24 claims
- 2287US8291201B2Dynamic merging of pipeline stages in an execution pipeline to reduce power consumptionSCHWINN STEPHEN JOSEPH·Filed 2008·Granted Oct 16, 2012·21 cites·25 claims
- 2386US10067556B2Branch prediction with power usage prediction and controlIBM·Filed 2015·Granted Sep 4, 2018·4 cites·19 claims
- 2486US9652239B2Instruction set architecture with opcode lookup using memory attributeIBM·Filed 2016·Granted May 16, 2017·3 cites·12 claims
- 2586US9652238B2Instruction set architecture with opcode lookup using memory attributeIBM·Filed 2016·Granted May 16, 2017·3 cites·20 claims
- 2686US9594557B2Floating point execution unit for calculating packed sum of absolute differencesIBM·Filed 2016·Granted Mar 14, 2017·3 cites·18 claims
- 2786US9594562B2Extensible execution unit interface architecture with multiple decode logic and multiple execution unitsIBM·Filed 2016·Granted Mar 14, 2017·3 cites·20 claims
- 2886US9594556B2Floating point execution unit for calculating packed sum of absolute differencesIBM·Filed 2016·Granted Mar 14, 2017·3 cites·20 claims
- 2986US9542184B2Local instruction loop buffer utilizing execution unit register fileIBM·Filed 2016·Granted Jan 10, 2017·3 cites·15 claims
- 3086US9501279B2Local instruction loop buffer utilizing execution unit register fileIBM·Filed 2016·Granted Nov 22, 2016·3 cites·9 claims
- 3186US9317291B2Local instruction loop buffer utilizing execution unit register fileIBM·Filed 2013·Granted Apr 19, 2016·6 cites·8 claims
- 3286US8930432B2Floating point execution unit with fixed point functionalityHICKEY MARK J·Filed 2011·Granted Jan 6, 2015·10 cites·22 claims
- 3386US8412980B2Fault tolerant stability critical execution checking using redundant execution pipelinesHICKEY MARK J·Filed 2010·Granted Apr 2, 2013·9 cites·19 claims
- 3485US9405536B2Floating point execution unit for calculating packed sum of absolute differencesIBM·Filed 2015·Granted Aug 2, 2016·3 cites·4 claims
- 3585US8707094B2Fault tolerant stability critical execution checking using redundant execution pipelinesIBM·Filed 2013·Granted Apr 22, 2014·7 cites·20 claims
- 3684US9329870B2Extensible execution unit interface architecture with multiple decode logic and multiple execution unitsIBM·Filed 2013·Granted May 3, 2016·5 cites·10 claims
- 3784US9317294B2Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing coreIBM·Filed 2012·Granted Apr 19, 2016·6 cites·22 claims
- 3884US9032191B2Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levelsMUFF ADAM J·Filed 2012·Granted May 12, 2015·8 cites·25 claims
- 3984US8954755B2Memory address translation-based data encryption with integrated encryption engineMUFF ADAM J·Filed 2012·Granted Feb 10, 2015·7 cites·25 claims
- 4084US8514232B2Propagating shared state changes to multiple threads within a multithreaded processing environmentMEJDRICH ERIC O·Filed 2010·Granted Aug 20, 2013·8 cites·25 claims
- 4184US7926009B2Dual independent and shared resource vector execution units with shared register fileIBM·Filed 2007·Granted Apr 12, 2011·11 cites·6 claims
- 4283US9507599B2Instruction set architecture with extensible register addressingGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 29, 2016·6 cites·23 claims
- 4383US8719455B2DMA-based acceleration of command push buffer between host and target devicesMEJDRICH ERIC O·Filed 2010·Granted May 6, 2014·7 cites·23 claims
- 4482US9189051B2Power reduction by minimizing bit transitions in the hamming distances of encoded communicationsIBM·Filed 2012·Granted Nov 17, 2015·5 cites·8 claims
- 4582US9170954B2Translation management instructions for updating address translation data structures in remote processing nodesIBM·Filed 2012·Granted Oct 27, 2015·5 cites·17 claims
- 4681US9223753B2Dynamic range adjusting floating point execution unitIBM·Filed 2013·Granted Dec 29, 2015·5 cites·21 claims
- 4781US8935694B2System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructionsMUFF ADAM J·Filed 2012·Granted Jan 13, 2015·6 cites·23 claims
- 4880US9251116B2Direct interthread communication dataport pack/unpack and load/saveMUFF ADAM J·Filed 2011·Granted Feb 2, 2016·6 cites·23 claims
- 4980US8692825B2Parallelized streaming accelerated data structure generationMEJDRICH ERIC O·Filed 2010·Granted Apr 8, 2014·6 cites·12 claims
- 5080US8627329B2Multithreaded physics engine with predictive load balancingMEJDRICH ERIC O·Filed 2010·Granted Jan 7, 2014·6 cites·1 claims
Showing the top 50 of 134 patent records by PatentIndex Score.
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