Inventor · disambiguated record
Sam S. Garcia
Also filed as: GARCIA SAM · GARCIA SAM S
15 granted patents·5 pending applications·460 citations·filing 1996–2011
93Inventor score
Files withFREESCALE SEMICONDUCTOR INC7MOTOROLA INC6MATHEW VARUGHESE2CHATTERJEE RITWIK1HARRISON MICHAEL G1
Top patents by PatentIndex Score
20 records- 0189US6093966ASemiconductor device with a copper barrier layer and formation thereofMOTOROLA INC·Filed 1998·Granted Jul 25, 2000·116 cites·31 claims
- 0288US6187682B1Inert plasma gas surface cleaning process performed insitu with physical vapor deposition (PVD) of a layer of materialMOTOROLA INC·Filed 1998·Granted Feb 13, 2001·94 cites·21 claims
- 0388US5801098AMethod of decreasing resistivity in an electrically conductive layerMOTOROLA INC·Filed 1996·Granted Sep 1, 1998·103 cites·20 claims
- 0485US6924232B2Semiconductor process and composition for forming a barrier material overlying copperFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Aug 2, 2005·36 cites·20 claims
- 0583US7422979B2Method of forming a semiconductor device having a diffusion barrier stack and structure thereofFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Sep 9, 2008·14 cites·10 claims
- 0682US8168468B2Method of making a semiconductor device including a bridgeable materialMATHEW VARUGHESE·Filed 2008·Granted May 1, 2012·11 cites·20 claims
- 0782US6294458B1Semiconductor device adhesive layer structure and process for forming structureMOTOROLA INC·Filed 2000·Granted Sep 25, 2001·36 cites·24 claims
- 0873US7572723B2Micropad for bonding and a method thereforFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Aug 11, 2009·6 cites·18 claims
- 0972US6451181B1Method of forming a semiconductor device barrier layerMOTOROLA INC·Filed 1999·Granted Sep 17, 2002·36 cites·6 claims
- 1063US7410544B2Method for cleaning electroless process tankFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Aug 12, 2008·1 cites·19 claims
- 1162US7807572B2Micropad formation for a semiconductorFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Oct 5, 2010·2 cites·20 claims
- 1261US8003517B2Method for forming interconnects for 3-D applicationsFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Aug 23, 2011·2 cites·19 claims
- 1358US7932175B2Method to form a viaFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 26, 2011·1 cites·36 claims
- 1455US8586474B2Method to form a viaCHATTERJEE RITWIK·Filed 2011·Granted Nov 19, 2013·1 cites·20 claims
- 1545US6476623B1Percent backsputtering as a control parameter for metallizationMOTOROLA INC·Filed 2000·Granted Nov 5, 2002·1 cites·12 claims
- 1639US2002092763A1Method for forming a barrier layer for use in a copper interconnectFiled 2002·Application pending·0 cites
- 1739US2006270234A1Method and composition for preparing a semiconductor surface for deposition of a barrier materialMATHEW VARUGHESE·Filed 2005·Application pending·0 cites
- 1836US2007049008A1Method for forming a capping layer on a semiconductor deviceMARTIN GERALD A·Filed 2005·Application pending·0 cites
- 1935US2005266664A1Method for forming a fully silicided semiconductor deviceHARRISON MICHAEL G·Filed 2004·Application pending·0 cites
- 2029US2003134504A1Method of making an inlaid structure in a semiconductor deviceFiled 2002·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →