Inventor · disambiguated record
Joseph Sheredy
Also filed as: SHEREDY JOSEPH
10 granted patents·125 citations·filing 2002–2018
90Inventor score
Top patents by PatentIndex Score
10 records- 0196US7948798B1Mixed multi-level cell and single level cell storage deviceMARVELL INT LTD·Filed 2009·Granted May 24, 2011·59 cites·11 claims
- 0295US10209902B1Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the dataMARVELL INT LTD·Filed 2018·Granted Feb 19, 2019·11 cites·20 claims
- 0389US9898212B1Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the dataMARVELL INT LTD·Filed 2017·Granted Feb 20, 2018·4 cites·20 claims
- 0487US9244834B2Method and apparatus for selecting a memory block for writing data, based on a predicted frequency of updating the dataMARVELL INT LTD·Filed 2013·Granted Jan 26, 2016·6 cites·17 claims
- 0581US8495320B1Method and apparatus for storing data in a flash memory including single level memory cells and multi level memory cellsSHEREDY JOSEPH·Filed 2012·Granted Jul 23, 2013·4 cites·18 claims
- 0681US8135913B1Mixed multi-level cell and single level cell storage deviceSHEREDY JOSEPH·Filed 2011·Granted Mar 13, 2012·5 cites·19 claims
- 0774US7308530B1Architecture for a data storage deviceMARVELL INT LTD·Filed 2003·Granted Dec 11, 2007·24 cites·16 claims
- 0859US7062423B1Method and apparatus for testing a system on a chip (SOC) integrated circuit comprising a hard disk controller and read channelMARVELL INT LTD·Filed 2002·Granted Jun 13, 2006·9 cites·32 claims
- 0954US8086935B1Soft error correction for a data storage mechanismSHEREDY JOSEPH·Filed 2007·Granted Dec 27, 2011·3 cites·45 claims
- 1039US7870342B2Line cache controller with lookaheadMARVELL INT LTD·Filed 2003·Granted Jan 11, 2011·0 cites·29 claims
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