Inventor

TSAI JR-SHIAN

US69 patents

⚠️ This page may combine multiple inventors who share the name “TSAI JR-SHIAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI JR-SHIAN

INTEL CORP

Encoded inline capabilities

Power saving techniques for use in communication systems, networks, and devices

Function as a service (FaaS) system enhancements

Technologies for secure inter-virtual-machine shared memory communication

Service discovery architecture and method for wireless networks

Methods and apparatus for a keying mechanism for end-to-end service control protection

Methods and apparatus for a paging mechanism within wireless networks including multiple access points

Multi-core communication acceleration using hardware queue device

Interference adaptation apparatus, systems, and methods

Adaptive interrupt coalescing for energy efficient mobile platforms

Method and apparatus for accelerating VM-to-VM network traffic using CPU cache

Techniques for routing packets between virtual machines

Technologies for a distributed hardware queue manager

Adaptively disabling and enabling sleep states for power and performance

Aperture access processors, methods, systems, and instructions

Generating, at least in part, and/or receiving, at least in part, at least one request

Aperture access processors, methods, systems, and instructions

Intelligent receive buffer management to optimize idle state residency

Protected paging indication mechanism within wireless networks

Encoded inline capabilities

Processor and method implementing a cacheline demote machine instruction

Technologies for GPU assisted network traffic monitoring and analysis

Data plane semantics for software virtual switches

Technologies for GPU assisted network traffic monitoring and analysis

Coordinating device and application break events for platform power saving

Multi-core communication acceleration using hardware queue device

Technologies for offloading network packet processing to a GPU

Hardware offload circuitry

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

WANG REN

Conserving power in a computer system

Method and apparatus for I/O devices assisted platform power management

Coordinating device and application break events for platform power saving

Packet buffering based at least in part upon packet receipt time interval weighted moving average

Generating, at least in part, and/or receiving, at least in part, at least one request

Packet processing approach to improve performance and energy efficiency for software routers

Generating, at least in part, and/or receiving, at least in part, at least one request

Power management using relative energy break-even time

Dynamically entering low power states during active workloads

Techniques for managing power consumption state of a processor involving use of latency tolerance report value

TSAI JR-SHIAN

Buffering techniques for power management

Techniques for communications power management based on system states

Techniques for collaborative power management for heterogeneous networks

Techniques for communications based power management

HSIN CHIH-FAN

DMA (direct memory access) coalescing

Method and apparatus for modifying power management configuration of a computer to accommodate a packet processing latency policy associated with a pattern

Method and apparatus for performing energy-efficient network packet processing in a multi processor core system

QI EMILY H

Mobile platform tracking in wireless networks

TSAI JR SHIAN

Techniques for collaborative power management for heterogeneous networks

GOBRIEL SAMEH

Power saving system, method and apparatus for a wireless device

MIN ALEXANDER W

Joint optimization of processor frequencies and system sleep states